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Overview
This example VI was written to show the easiest way to synchronize two PXI S series devices that are using Warp Mode.
Description
For this example there is a master device and a slave device. The master device generates the clock using an onboard counter, or if selected, receives an external clock signal, and routes the clock along the PXI backplane. With slight modifications to the block diagram this VI could be used with PCI devices sharing a clock along a configured RTSI cable.
Requirements
Software:
Hardware:
Steps to Implement or Execute Code
Additional Information or References
VI Snippet
**This document has been updated to meet the current required format for the NI Code Exchange.**
Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.