Synchronization Performance between PXIe System and cRIO-904X series under IEEE 1588

[YueLiao]

Description

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In order to figure out the synchronization performance under cross platform circumstances, this article use IEEE 1588-2008 protocol as synchronization time reference to implement a sync DAQ task between a PXIe platform and a cRIO-904X platform.

 

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How to Use

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Set up IEEE 1588 time synchronization environment between two platforms

1. PXI-6683 as master device, cRIO-904X as slave device;

Connection:
PXI-6683 —— Ethernet Cable —— cRIO-904X Port 1;
PXI-6683 PFI0 —— PXIe DAQ PFI0 & cRIO digital module PFI0; (Start Trigger);
PXIe Arb Gen CH0 —— PXIe DAQ AI1 & cRIO DAQ AI0; (Sine Wave Signal Source);

2. Set up IEEE 1588 time reference configuration in NI-MAX:

3. Use LabVIEW example [Monitor Synchronization.vi], we can monitor the time offset between the slave device and the time reference of the master device.
From the below figure, we can see, when there is no DAQ task running on both system, the synchronization performance can be with in 1us. 

Synchronization Performance Benchmark on DAQ Task Running Circumstance

1. Confirm correct cable connection;
2. Set up PXIe Arb Generator and output a 1kHz, 2Vpp Sine Wave with load impendence set to 10GΩ;

cRIO steps:
3. Configure a start trigger source via digital module;
4. Set sampling rate at 100k, and number of samples as 1, in order to get each time stamp for every sample;
5. extract the first 100 data after triggering for display and comparison;

PXI steps:
6. Combine DAQmx continuous input example with NI-Sync example for PXI DAQ task;
7. PXI-6683 generate sampling clock and route it to PXIe DAQ as AI sampling clock from chassis backplane;

8. At the same time, this clock is also used by PXI-6683 itself as the reference clock to record the current IEEE 1588 timestamp.
Thus, the data collected by the PXI terminal can correspond to the synchronous time signal of 1588.

9. cRIO-904X uses the system clock in the controller directly as the AI sampling clock, since this clock was tamed by the clock from PXI-6683.
Therefore, the data collected by cRIO also corresponds to the synchronous time signal of 1588.
(The system Time of all Linux Real Time operating systems can be synchronized and tamed using the same method to establish the master-slave relationship in the LAN, but the synchronization progress varies with different hardware conditions.)

10. 5 seconds after running the program, the PXI-6683 PFI0 port will generate digital pulse as a start trigger to simultaneously trigger the AI acquisition of PXI DAQ and cRIO DAQ, and then record 100 data sampling points.

11. [Time compare.vi] is used for data comparison. The collected data is transmitted to the upper computer through network shared variables and presented in the same waveform graph as follows:

Resolution:

1. The synchronization performance between THE PXI system and the CRIO-904X system based on IEEE 1588 is stable at the sub-microsecond level, and the clock offset is within the error range of 100ns.

cRIO-903x series controller has been tested before. The same method can only be controlled in sub-millisecond level, and the clock offset fluctuates within 10us.

2. When running a DAQ task on both platforms, the time offset between sampling time points is less than 500ns, because the DAQ acquisition task is running at same time, so the jitter of clock synchronization accuracy increases.

3. Both platforms collect data from the same signal source, so theoretically the two waveforms should completely coincide. However, due to trigger time offset, signal line length difference, sampling rate difference and other factors, waveform may be different in phase. The current phase difference is 3.7°, which translates into a time is about 10us.1. The synchronization performance between THE PXI system and the CRIO-904X system based on IEEE 1588 is stable at the sub-microsecond level, and the clock offset is within the error range of 100ns.

cRIO-903x series controller has been tested before. The same method can only be controlled in sub-millisecond level, and the clock offset fluctuates within 10us.

2. When running a DAQ task on both platforms, the time offset between sampling time points is less than 500ns, because the DAQ acquisition task is running at same time, so the jitter of clock synchronization accuracy increases.

3. Both platforms collect data from the same signal source, so theoretically the two waveforms should completely coincide. However, due to trigger time offset, signal line length difference, sampling rate difference and other factors, waveform may be different in phase. The current phase difference is 3.7°, which translates into a time is about 10us.

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Additional Information

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Hardware:

PXIe: PXIe-1062 chassis, PXIe-8135 controller with Windows 10, PXI-6683 IEEE 1588 Sync Module, PXIe-5442, PXIe-6368;
cRIO: cRIO-9049 Real-Time Mode, NI-9215, NI-9401;

Software:

[PXI]: LabVIEW 2020; LabVIEW Real Time Module 2020; NI-DAQmx 20.1; NI-FGEN; NI-Sync 20.1
[cRIO]: Linux RT System Image 20.6; NI-DAQmx 20.1; NI-Sync 20.1;

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Related Links

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• Configuring IEEE 1588 Synchronization With the NI PXI-668x Timing and Synchronization Module
• Using NI-TimeSync to Configure IEEE 1588 and 802.1AS Time References
• Monitor and Configure Time Synchronization on Embedded Devices

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