Contains a function block (IP core) for LabVIEW FPGA that generates pulses of variable frequency and duty cycle. Also includes example code that that demonstrates host interface data scaling options for units of seconds, Hz, or percent duty cycle. Works with any C Series digital output module. Example is compiled for an NI 9474 module in slot 4 and a cRIO-9103 chassis (4 slot, 3M gate). Demonstrates use of I/O node error checking to detect a missing or incorrectly installed module. Demonstrates use of clock and elapsed time outputs for triggering other FPGA loops.
PULSE WIDTH MODULATION IP CORE
Generates a digital pulse width modulation (PWM) signal. PWM signals are useful for driving loads such as motors and proportional valves because the average voltage supplied is equal to the PWM duty cycle. The output of this function can be connected to C Series digital output modules. This function is designed for use in LabVIEW FPGA.
At the beginning of each cycle the digital output is turned on. The digital output is left on for the amount of time specified by the PWM Duty Cycle (Ticks) input. The cycle repeats when the amount of time specified by the PWM Period (Ticks) has elapsed. The FPGA tick counter is used to calculate elapsed time. By default, one tick is equal to 25 nanoseconds (40 MHz), so a PWM Period (Ticks) of 40,000 results in a 1 kHz PWM signal. The PWM Duty Cycle (Ticks) input is a signed integer, but the sign of the value is ignored.
This subVI is reentrant, so you can place multiple instances of the function in a LabVIEW FPGA application and they each will operate independently.
To obtain the highest timing resolution when using this function in a loop, you can perform digital output I/O operations only when the PWM DO value has changed (rather than on every cycle). To do this, wire the Changed? output to the conditional terminal on a case statement and perform the I/O operation when the case statement is True. If the duty cycle is 0 or 100%, the Changed? output will strobe true once per PWM cycle at the beginning of the cycle.
The PWM Clock signal is a 50% duty cycle square wave signal that can be used to synchronize other loops with the beginning (rising edge) or middle (falling edge) of the PWM cycle.
The Telapsed (Ticks) signal can be used to trigger other operations at particular time in the PWM cycle. For instance, you could use this signal to trigger an analog input operation to occur once per PWM cycle at a programmable time within the PWM cycle. This counter resets back to 0 at the beginning of every PWM cycle.
The Min Period (Ticks) signal is used to limit the PWM Period to prevent switching at frequencies that could damage the output MOSFETs in a digital output device. By default Min Period (Ticks) is set to 1000 ticks, which limits the PWM switching frequency to 40 kHz.
PWM Period (Ticks)- Total width of the pulse (inverse of the "PWM Frequency")
PWM Duty Cycle (Ticks)- Time for which signal output stays True
Min Period (Ticks)- The minimum allowed value for the PWM Period
PWM DO- Digital PWM signal that can be connected to a digital output channel I/O node
PWM Clock- 50% duty cycle clock signal that can be used for synchronizing other loops
Changed?- Value is True for one iteration when the PWM DO value has changed, or at the beginning of the PWM cycle if the duty cycle is 0 or 100%
Telapsed- The amount of time elapsed during the current PWM cycle
The formulas below can be used for scaling from units of Hz, seconds, or percent duty cycle in the real-time host interface application. These formulas assume a 40 MHz (40,000,000 Ticks/sec) FPGA clock rate.
PWM Period (Ticks) = 40,000,000 / PWM Period (Hz)
PWM Period (Ticks) = 40,000,000 * PWM Period (sec)
PWM Duty Cycle (Ticks) = PWM Period
Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.