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This VI contains an event counter that increments on every falling edge of the input trigger signal (PB1). To reset the value of the counter, use the designated asynchronous reset button (PB2) on the board.
This VI contains an event counter that increments on the hardware selected edge of the input signal, either rising or falling. To reset the value of the counter, use the designated reset button (PB2) on the board.
This VI uses the quadrature encoder hardware on the evaluation board daughter card to count pulses on the encoder. The VI decodes the A and B pulses and an 8-bit count, displays it on the Front Panel as well as in binary on the evaluation board LEDs,and shows the current count position of the encoder. Use the reset button on the VI front panel to reinitialize the quadrature encoder count to zero.
This VI interprets a quadrature encoder input using the A and B signals and also asynchronously saves the current position value on every valid index state. This means that the position value is stored each time a particular configuration of inputs is seen. In this case, a valid index state is defined when Line A, Line B, and Input Z are all low.
This VI performs a two edge separation measurement between the push buttons PB1 and PB2. The output is the difference in milliseconds between rising edges of PB1 and PB2.
This VI generates a pulse width modulated output with variable high and low periods. The program uses the potentiometer to vary the duty cycle from 0% to 100%. In addition, use the onboard Function Generator frequency toggle switch to select between .5 Hz and 100 Hz PWM frequencies. The result of the PWM is represented on the LEDs.
This VI is divided into two parts - PWM generation and PWM measurement. First, it generates a pulse train on a digital output according to low and high period controls. Next, it measures the same digital signal using a digital input and measures the high and low periods in software.
This VI is divided into two parts - PWM generation and PWM measurement. It first generates a pulse train on a digital output according to low and high period controls. Changes to these control values take place one full period following the assertion of the Load control. It then measures the same digital signal using a digital input to evaluate the high and low periods in software. The high and low period measurements are updated after the Latch control is asserted.
This VI demonstrates the functionality of a look-up table (LUT) using the eval kit hardware. It references a predefined table of values corresponding to a sine waveform. Then, it outputs the waveform on the six LEDs of the evaluation kit daughter board. The program uses the potentiometer on the daughter card to vary the frequency.
This application demonstrates the use of the Butterworth filter on the FPGA as well as FPGA to real-time processor communication. The FPGA generates a noisy sine wave and passes the waveform through an analog output. By using a loopback connection, the program reads the waveform back through an analog input and filters out the noise. The FPGA sends waveform data to the processor where it is formatted to display on a chart.
This VI creates an FPGA personality to emulate a hardware watchdog. If the watchdog timer is not reset prior to a software-defined expiration time (in milliseconds), an expiration indicator will show that the watchdog has timed out.
This application builds off of the FPGA personality created in the previous example. If the watchdog timer is not reset prior to a software-defined expiration time (in milliseconds), an expiration indicator will show that a timeout has occurred. This will trigger the real-time VI to display a dialog box on your user interface indicating the watchdog expired. This shows how the watchdog can be used to trigger interrupt code.
This application demonstrates the use of a Real-Time FIFO to deterministically communicate data between two loops running on the real-time processor. The first FIFO in this example contains control information while the second contains waveform data for display. A low priority loop reads waveform data and displays it on a graph while writing data to the control FIFO. A high priority loop writes waveform data to the data FIFO and regulates the waveform according to data on the control FIFO.
This application shows how to use TCP communication to transfer streaming data from a Real-Time target to a host computer. A TCP connection is opened between the targets. The data server on the Real-Time target generates waveform data and transfers it to the data client on the computer.
This application illustrates a TCP file transfer. An FPGA VI generates sine waveform data. The real-time processor reads a finite number of points from this FPGA- generated waveform and writes the data to a spreadsheet file on the target. The file is transmitted via TCP from the eval kit target to your host computer, which then reads the spreadsheet file and outputs the waveform to a front panel graph.
Download Additional Examples.zip below to get all of the examples found on this page in one zip file.
Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.