(LV FPGA) Timing Violations When Using DIO Nodes in Both While Loops and SCTL's

[DanRichards]

Functional Description

This may not seem like much at first glance, but it helps get around a hardware limitation in LabVIEW FPGA. If you are calling a DIO node in a single-cycle timed loop (SCTL) and you need to also write a value to a digital line from a normal while loop, LabVIEW FPGA will give you a compilation error, saying that you have failed to meet timing constraints in your intended code. The way to get around that is to have an SCTL whose state is triggered from the While Loop.

Caveats and Additional Notes

This is very basic functionality but it can be expanded upon. For example, you might have multiple states that are affected programmatically, too. This VI is just intended to promote thinking about what the compiler will accept.