Description
Description-Separate-1Overview:
The bitfiles linked below provide simple discrete (digital) IO and PWM generation/measurement personalities for supported R-Series modules. Each personality enables individual configuration of all IO for the targeted R-Series modules on a line-by-line basis. All IO updates at a rate of once per tick of the 40 MHz Onboard Clock. This IP is intended for use with the Veristand FPGA Addon custom device, however it can also be used for other applications. If you plan to use these personalities outside of the intended use case, you must initialize your code by acknowledging the interrupt number 30 as a handshake mechanism to begin execution.
The configuration and result registers are named to indicate their corresponding digital line, bank, and physical connector. For example, “C0B1L2.ActiveEdge” corresponds to the ActiveEdge parameter for Line 2 of Bank 1 in Connector 0.
Supported Hardware:
- PXIe-7820
- PXIe-7821
- PXIe-7822
Discrete Generation:
Description
The discrete generation personalities enable you to use supported R-Series modules to generate digital signals on the bank (port) level.
Configuration Registers
- Value: Sets the value of the digital signal in the corresponding bank.
Discrete Measurement:
Description
The discrete measurement personalities enable you to use supported R-Series modules to measure digital signals on the bank (port) level. Readings can be further decomposed into line-by-line measurements by enabling bitpacking in the Veristand FPGA Addon Custom Device.
Configuration Registers
- Reading: Indicates the measured value of the digital signal in the corresponding bank.
PWM Generation:
Description
The PWM generation personalities enable you to use supported R-Series modules for PWM generation. When used, each digital line on the R-Series module can be used to generate a unique PWM signal.
Configuration Registers
- ActiveTicks: Specifies the number of ticks in each period of the PWM waveform will be in the active state.
- InactiveTicks: Specifies the number of ticks in each period of the PWM waveform will be in the inactive state.
- ActiveEdge: Specifies the edge transition upon which the active interval begins. When ActiveEdge is set to 0, the active interval will begin on each falling edge and end with each rising edge. When ActiveEdge is set to 1, the active interval will begin on each rising edge and end with each falling edge.
PWM Measurement:
Description
The PWM measurement personalities enable you to use supported R-Series modules for measurement of PWM signals. When used, each digital line on the R-Series module can be utilized for measurement.
Configuration Registers
- ActiveEdge: Specifies the edge transition upon which the active interval begins. When ActiveEdge is set to 0, the active interval will begin on each falling edge and end with each rising edge. When ActiveEdge is set to 1, the active interval will begin on each rising edge and end with each falling edge.
- Timeout: Specifies the maximum number of ticks to wait for a full PWM cycle to complete. When the acquisition time exceeds the number of ticks specified with the timeout, the result registers will all return 0.
Result Registers
- ActiveTicks: Indicates the number of FPGA ticks over which the PWM signal has been measured to be in the “active” state since the previous timeout.
- InactiveTicks: Indicates the number of FPGA ticks over which the PWM signal has been measured to be in the “inactive” state since the previous timeout.
Description-Separate-2
