Importing a .vhd File into the FPGA HDL Node (deprecated)

[Andrew_E]

Overview

This example demonstrates how to include VHDL code in LabVIEW FPGA with the HDL Interface Node.

Description

This example demonstrates how to import the functionality of IP in a .vhd file into LV FPGA using the HDL node. It replicates a simple and function that is coded in VHDL and imported into LV using an HDL Node.

 

Requirements

 Software

• LabVIEW Full Development System 2012 (or compatible)
• LabVIEW FPGA Module 2012 (or compatible)

 Hardware

• No hardware is necessary to use this example VI

Steps to Implement or Execute Code

1. Download and open the attached ZIP-file
2. Open the VI and follow the instructions on the Front Panel

Additional Information or References

Note:
Keep in mind that the HDL Interface Node was replaced with the IP Integration Node in LabVIEW 2010.
The HDL Interface Node should only be used if you must use LabVIEW 2010 or earlier or if you already use it in an existing application.

**The code for this example has been edited to meet the new Community Example Style Guidelines. The edited copy is marked with the text ‘NIVerified’. Read here for more information about the new Example Guidelines and Community Platform.**

[Andrew_E]

Overview

This example demonstrates how to include VHDL code in LabVIEW FPGA with the HDL Interface Node.

Description

This example demonstrates how to import the functionality of IP in a .vhd file into LV FPGA using the HDL node. It replicates a simple and function that is coded in VHDL and imported into LV using an HDL Node.

 

Requirements

 Software

• LabVIEW Full Development System 2012 (or compatible)
• LabVIEW FPGA Module 2012 (or compatible)

 Hardware

• No hardware is necessary to use this example VI

Steps to Implement or Execute Code

1. Download and open the attached ZIP-file
2. Open the VI and follow the instructions on the Front Panel

Additional Information or References

Note:
Keep in mind that the HDL Interface Node was replaced with the IP Integration Node in LabVIEW 2010.
The HDL Interface Node should only be used if you must use LabVIEW 2010 or earlier or if you already use it in an existing application.

**The code for this example has been edited to meet the new Community Example Style Guidelines. The edited copy is marked with the text ‘NIVerified’. Read here for more information about the new Example Guidelines and Community Platform.**

[Andrew_E]

Overview

This example demonstrates how to include VHDL code in LabVIEW FPGA with the HDL Interface Node.

Description

This example demonstrates how to import the functionality of IP in a .vhd file into LV FPGA using the HDL node. It replicates a simple and function that is coded in VHDL and imported into LV using an HDL Node.

 

Requirements

 Software

• LabVIEW Full Development System 2012 (or compatible)
• LabVIEW FPGA Module 2012 (or compatible)

 Hardware

• No hardware is necessary to use this example VI

Steps to Implement or Execute Code

1. Download and open the attached ZIP-file
2. Open the VI and follow the instructions on the Front Panel

Additional Information or References

Note:
Keep in mind that the HDL Interface Node was replaced with the IP Integration Node in LabVIEW 2010.
The HDL Interface Node should only be used if you must use LabVIEW 2010 or earlier or if you already use it in an existing application.

**The code for this example has been edited to meet the new Community Example Style Guidelines. The edited copy is marked with the text ‘NIVerified’. Read here for more information about the new Example Guidelines and Community Platform.**

[Andrew_E]

Overview

This example demonstrates how to include VHDL code in LabVIEW FPGA with the HDL Interface Node.

Description

This example demonstrates how to import the functionality of IP in a .vhd file into LV FPGA using the HDL node. It replicates a simple and function that is coded in VHDL and imported into LV using an HDL Node.

 

Requirements

 Software

• LabVIEW Full Development System 2012 (or compatible)
• LabVIEW FPGA Module 2012 (or compatible)

 Hardware

• No hardware is necessary to use this example VI

Steps to Implement or Execute Code

1. Download and open the attached ZIP-file
2. Open the VI and follow the instructions on the Front Panel

Additional Information or References

Note:
Keep in mind that the HDL Interface Node was replaced with the IP Integration Node in LabVIEW 2010.
The HDL Interface Node should only be used if you must use LabVIEW 2010 or earlier or if you already use it in an existing application.

**The code for this example has been edited to meet the new Community Example Style Guidelines. The edited copy is marked with the text ‘NIVerified’. Read here for more information about the new Example Guidelines and Community Platform.**

[Andrew_E]

Overview

This example demonstrates how to include VHDL code in LabVIEW FPGA with the HDL Interface Node.

Description

This example demonstrates how to import the functionality of IP in a .vhd file into LV FPGA using the HDL node. It replicates a simple and function that is coded in VHDL and imported into LV using an HDL Node.

 

Requirements

 Software

• LabVIEW Full Development System 2012 (or compatible)
• LabVIEW FPGA Module 2012 (or compatible)

 Hardware

• No hardware is necessary to use this example VI

Steps to Implement or Execute Code

1. Download and open the attached ZIP-file
2. Open the VI and follow the instructions on the Front Panel

Additional Information or References

Note:
Keep in mind that the HDL Interface Node was replaced with the IP Integration Node in LabVIEW 2010.
The HDL Interface Node should only be used if you must use LabVIEW 2010 or earlier or if you already use it in an existing application.

**The code for this example has been edited to meet the new Community Example Style Guidelines. The edited copy is marked with the text ‘NIVerified’. Read here for more information about the new Example Guidelines and Community Platform.**

[maheshkumar0459]

Hi Andrew,

I am able to integrate VHDL code into LabVIEW using IP integration node. If VHDL code is only a VHDL code it is working fine but if i use any xilinx ip then output is always '0' or false is coming. I didn't understand why this is happening. Please let me know the reason why it is happening.

Thanks & Regards,

Mahesh