This example contains an IRIG-B generator and decoder implemented in LabVIEW FPGA. The generator and decoder are implemented in two different LabVIEW FPGA VIs and are intended to run on different FPGA targets. The host VI downloads each FPGA personality to a different card and communicates with both to output an IRIG-B timing signal on one card and read it back in with the other card. The example is set up for a PXI-7811 and a PXI-7831R card, but the FPGA VIs and host VI can be easily updated for any of the RIO hardware targets.
The IRIG-B standard implemented in this example is the IRIG-B 000 variant.
Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.
I think there is a bug in the generation part. From what I can understand it does not use 40 and 80 days as shown in the figure below, those bits are always false in the VI parse days.
