This example shows how to correctly implement a DMA transfer mechanism containing the possibility of overflow (too much data for the buffer to handle) or underflow (not enough data is being sent). The implementation makes sure the buffer is never full on the FPGA side for overflow and never times out waiting for data on the host side for underflow. In order to guarantee lossless data transfer between an FPGA and Host overflow and underflow conditions must not occur.
Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.
