Description
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Pulse Width Modulation (PWM) can produce an output that has limited rate and dynamic range. By using pulse density, the same proportion of time is spent in each state as in PWM, but the time spent in each state is more evenly distributed. This makes filtering easier and the bandwidth can increase too. This is the principle widely used in Pulse Density Modulation.
This code is a variation on that theme where the actual on and off times are varied to accommodate small variations in the output demand. The result is that there is no need for any intermittent, step updates, resulting in a very smooth response.
This a a little different from PDM but it's closer to PDM than PWM. Perhaps a more accurate name would be variable pulse width modulation (vPWM).
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How to Use
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The code is presented as a VI "PDM (SCTL)" that should be placed inside a single cycle timed loop (SCTL). It is deceptively simple. There are two inputs. One is the duty cycle, which should be between 0 and 1. The other is the minimum number of ticks for which the output state cannot change. If the output is switching a FET for example, there will be a trade off between the speed of the device and how much time the device is transitioning between states. Similarly, there may be a limit to the rate at which a FPGA card may be able to switch it's output. A value of 40 when using the default base clock will result in a minimum on or off time of 1us. The length of any given pulse will not be less than this but it may increase incrementally at the resolution of the clock in use.
There is a simple VI that demonstrates how to use the subVI on an FPGA target. It's called "FPGA PDM Example at 100MHz.vi"
There is also a host based vi "Demo PDM.vi" that allows you to play with the PDM code and get an understanding of what it's doing. This also includes a lowpass filter so that you can verify the output pulse stream is correct.
The filenames use the name "PDM" as it was how I started writing the code, but this is not a PDM implementation. At some point I'll update the files and change the naming, probably substituting "vPWM" for "PDM".
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