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Overview
This example uses LabVIEW FPGA to generate a continuous pulse train of a variable frequency and duty cycle. The pulse train is generated on the FPGA and is output from a cRIO digital output module.
Description
Pulse train A repetitive series of pulses, separated in time by a fixed and often constant interval. The duration of each pulse and its duty cycle are also often made constant. In this example we are generating a digital continuous pulse train of a variable frequency and duty cycle. The pulse train is generated on the FPGA and is output from a cRIO digital output module.
Requirements
LabVIEW 2015 or compatible
LabVIEW 2015 FPGA or compatible
LabVIEW 2015 RT or compatible
NI RIO driver
Steps to Implement or Execute Code
In the cRIO Pulse Gen (Host) VI
Additional Information or References
cRIO Pulse Gen (HOST) VI Block Diagram
cRIO Pulse Gen (FPGA) VI Block Diagram
**This document has been updated to meet the current required format for the NI Code Exchange. **
Regards,
Dan King
Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.