NI DDK with PXIe-6363 board

[Changseung]

Does anyone try/use DDK with PXIe-6363 board? For me, Finite sampling (never stop), reference triggering, external gating doesn't work.

[Joelbob]

Hi Changseung,

The PXIe-6363 should work with the DDK. Can you describe more what you have tried so far and how you have your device configured (what are you using as a trigger, etc.)?

Joel

[Changseung]

Hi Joel

Thank you very much for your replying.

Bug1: Finite sampling: it doesn’t stop after number of sample acquired.

             The configuration of test code is exactly same as aiex2.cpp from NIMHDDK (NI Measurement Hardware Driver Development Kit)

Bug2: reference trigger: reference triggering doesn’t work.

             The configuration of test code is exactly same as aiex4.cpp from NIMHDDK (NI Measurement Hardware Driver Development Kit)

Bug3: External gate doesn’t’ work

              I have configured correctly AI_Trigger_Select_Register (AI_External_Gate_Select bits) but never stopped/paused DAQ.

Anyhow, I will contact officially NI DAQ R&D through different communication channel. 

Thank you very much!!!

Changseung

[Joelbob]

Hi Changseung,

I'm a manager in NI R&D and I'd like to see what we can do for you here. Since we expect the 6363 should just work there is a good chance there is something not quite right about the complete configuration. If you can provide us more details about what you have tried and what types of signals are connected we should be able to help you.

Regards,
Joel

[Changseung]

Hi, Joel

I am leading All NI open source driver development at ITER (International Thermonuclear Experimental Reactor) with supporting of NI R&D team and/or using resource of NI parteners.

The DAQ open source driver currently works well with PXIe-6368 board, PXIe-6356 and I have implemented PXIe-6363 support now.

The new open source driver works very well with PXIe-6363 board except three functions (finite sampling, reference trigger, external gate).

[Changseung]

i, Joel

I am leading All NI open source driver development at ITER (International Thermonuclear Experimental Reactor) with supporting of NI R&D team and/or using resource from NI partners.

The DAQ open source driver currently works well with PXIe-6368 board, PXIe-6356 and I have implemented PXIe-6363 support now.

The new open source driver works very well with PXIe-6363 board except three functions (finite sampling, reference trigger, external gate).

The system configuration I have used here is described below.

OS: RHEL 7.3 64 bits 

CPU: Industrial computer with PCIe-PXIe extension (NI PXIe-PCIe 8371)

PXI Chassis: PXIe-1065

DAQ board: PXIe-6363

1. Finite test configuration: The test configuration is exactly same as aiex2.cpp example.

* Example Features (! means highlighted, * means default)
* Device
* Operation : voltage measurement
* Channel
* Channels : ai0, ai1, ai2, ai3
* Scaling : Volts (*) or raw ADC codes
* ! Terminal config : RSE (*), differential, non-referenced single-ended
* Input range : +/- 10 V (*), +/- 5 V, +/- 2 V, +/- 1 V,
* +/- 500mV, +/- 200 mV, +/- 100 mV
* Timing
* ! Sample mode : finite
* ! Timing mode : hardware-timed
* ! Clock source : on-board oscillator
* ! Clock rate : 20 kHz sample clock; 200 kHz convert clock (MIO only)
* Trigger
* ! Start trigger : PFI0 (retriggerable digital rising edge)
* Reference trig : none
* Pause trigger : none
* Read Buffer
* Data transfer : programmed IO from FIFO
* Behavior
* Timeout : 10 seconds
*
* External Connections
* ai0:3 : voltages within +/- 10 V (*) or other specified range
* PFI0 : TTL start trigger
*
* Copyright 2011 National Instruments
* License: NATIONAL INSTRUMENTS SOFTWARE LICENSE AGREEMENT
* Refer to "MHDDK License Agreement.pdf" in the root of this distribution.
*

 2. reference triggering: The configuration is exactly same as aiex4.cpp

* Example Features (! means highlighted, * means default)
* Device
* Operation : voltage measurement
* Channel
* Channels : ai0
* Scaling : Volts (*) or raw ADC codes
* Terminal config : RSE (*), differential, non-referenced single-ended
* Input range : +/- 10 V (*), +/- 5 V, +/- 2 V, +/- 1 V,
* +/- 500mV, +/- 200 mV, +/- 100 mV
* Timing
* Sample mode : finite
* Timing mode : hardware-timed
* Clock source : on-board oscillator
* Clock rate : 500 Hz
* Clock polarity : rising edge (*) or falling edge
* Trigger
* Start trigger : software
* ! Reference trig : PFI0
* Pause trigger : none
* Read Buffer
* ! Data transfer : scatter-gather DMA ring
* ! DMA buffer : overwrite unread samples
* Behavior
* Timeout : 10 seconds
*
* External Connections
* ai0 : voltage within +/- 10 V (*) or other specified range
* PFI0 : TTL reference trigger
*
* Copyright 2011 National Instruments
* License: NATIONAL INSTRUMENTS SOFTWARE LICENSE AGREEMENT
* Refer to "MHDDK License Agreement.pdf" in the root of this distribution.
*
*/

 3. External gate: AI_Trigger_Select_Register (AI_External_Gate_Select bits)

AI_External_Gate_Select register configured (Gate_PFI1, value 2), all PFI ports are configured as INPUT direction.

AI_External_Gate_Polarity configured 0, 

I have provided 50% duty cycle at 1Hz on PFI1, configured 16 channel, differential mode, at 1MS/s sampling rate for 10 secnond. I expect 5MS total for 10 sececond but I have acquired 10MS for 10 second.

Please note that all these failed functions are working fine for simulatenous board.

I would appricate if NI confirms finite sampling, refernce trigger, external gate functions works fine with NI DDK and PXIe-6363 board.

Thank you in advance,

Changseung

[Steven_K.]

 Hey Changseung,

Joel asked me to take a look into this issue and I was able to successfully run both examples as expected on a 6363. I had a few questions about your setup:

1) What kind of signal are you feeding into PFI0 for aiex2.cpp and aiex4.cpp?

2) Can you post the source code for the modifications you have made? I'd like to see the exact code you are running.

Thanks,

Steven

[Changseung]

Hi, Steven

How are you~? Thank you for the posting

1. PFI1 terminal on PXI-6683H connected to PFI0 on PXIe-6363.

   When I configured finite sampling with PXIe-6363,  the start trigger works fine with PXIe-6363.

   Anyhow, I always use DMA data transfer for DAQ even if finite sampling.

   When I tested with PXIe-6386 board, bytesAvailable in the DMA buffer is always same as number of samples for finite but PXIe-6363 board, bytesAvailable in the DMA buffer is always much bigger than number of samples for finite (It seems to me DAQ never stop)

Therefore, I wonder when did you test finite sampling with PXIe-6363 board, how many samplesAvailable ?

samplesAvailable = device.AI.AI_Data_FIFO_Status_Register.readRegister(&status);

Is samplesAvailable same as number of finite sample what you configured?

Can you check that value of samplesAvailable is equal to samplesAvailable - number of finite samples after you read out number of finite samples in FIFO?

If it works, it seems to me I have to check my finite configuration again.

2. As you know I don't use NI HDDK directly, ITER has X series open source driver that referred your DDK example, configuration and so on. It will be very hard to you directly check ITER open source driver.

3. Have you tested with External gate with DDK?

Many thanks,

Changseung

[Steven_K.]

Hey Changseung,

I'm doing good! Thanks for asking.

1) Could you clarify exactly what you are trying to do? Are you you are trying to do finite acquisition with DMA? What kind of triggering are you trying to do, start or reference?

If you are basing your application on aiex4, the bytesAvailable will be larger than the number of samples you are trying to acquire. The way reference trigger works is we start acquiring before the trigger comes in to get the pretrigger samples. The DMA buffer is set to a circular buffer of the exact number of finite samples requested. We will override stale samples if we have not received the trigger. This will cause the bytesAvailable to be larger than the actual number of samples in the buffer. But since we limit the DMA buffer size to the number of samples we are looking to acquire, we get the correct number of samples. Here are source comments from aiex4 about this:

   // 2. If there is enough data in the buffer, read, scale, and print it
   else if (bytesAvailable >= dmaSizeInBytes)
   {
      // By allowing overwrites, the DMA buffer will skip to the newest data,
      // and since the buffer is exactly the size of the record (pre-trigger
      // samples + post-trigger samples), reading all of it at once returns
      // the entire record with the first pre-trigger sample as sample 1.
      dma->read(dmaSizeInBytes, reinterpret_cast<u8 *>(&rawData[0]), &bytesAvailable, allowOverwrite, &dataOverwritten, status);

2) While the whole source may not be useful, if you could make a smaller reproduction of the problems you are exhibiting, it would be a great help to get on the same page.

3) Can you explain which context you are using the external gate? Again any reduced source code would be helpful.

Thanks,