02-20-2006 02:19 PM
02-21-2006 06:05 PM
Hi dcfilter-
Both of the problems you're seeing are expected behavior- allow me to explain.
First, you can only refer to 32 lines in port 0 because each group of ports is organized on a seperate 8255 DIO chip. This means that you could theoretically address port0 as 32 bits, port 3 as 32 bits, port 6 as 32 bits, and port 9 as 32 bits, but there is no way to operate at any port widths wider than those. Because of the organization of the three ports onto a single chip, you have to be careful to initialize all ports as needed before you start operating on the individual ports because all ports on a given chip will re-initialize to default values whenever configuration is performed.
Hopefully this helps-
02-22-2006 10:40 AM
02-22-2006 11:47 AM
my first attempt to reply didn't go.
Each chip (M82C55A) has 3 registers PA0-7, PB0-7, PC0-7 for a toltal of 24 lines per chip and 4 chips per card for a total of 96 lines.the VI can span chips but only by one register. my problem is that i can only control the last port initalized. notice the last 2 lines. the port line of the VI doesn't seem to change the port.
Write to digital line issue: device 1, port 0, port width 24, line 23, state true, iteration 0, result NO error
first chip of 3 ports initalize
Write to digital line: device 1, port 3, port width 24, line 23, state true, iteration 0, result NO error
02-22-2006 12:40 PM