When using the clock on the req pin( pci-6534 ),active low, how can i make it stay low when not active?

[gmarz5]

I'm using an internal clock to transfer data on the rising edge of the req clock. The problem is that the req pin will go low in-between transfer and rise when starting to transfer causing a false edge and bad data transfer.

[RIO-Todd]

Greetings,

So the first rising edge of the REQ line (when re-starting the transfer) is not the first clock edge? I guess there is a period after starting the operation and before the REQ clock starts that the REQ line is high?

One thing I would suggest would be to look at the start-up state of the control lines on the PCI-6534. You can pull-up or pull-down the control lines by connecting the CPULL pin to either the +5V pin or a ground pin. Try connecting the CPULL pin to ground. This pin is for controlling the power up state of all of the control lines.

Hopefully this will help.

NI 653x User Manual

http://digital.ni.com/manuals.nsf/webAdvsearch/EDE443F5C700373A862569B90072D26F?OpenDocument

Regards,

Todd D.
NI Applications Engineer