Hello! I put the programs of the two modules of NI6581 and NI5782 in one project. In this project, I run two programs at the same time. The two pulses generated by NI6581 are 10MHZ and the pulse width is 12.5ns, and the two pulses generated by NI5782 are 10MHz and the pulse width is 10ns. I want these four pulses to be completely synchronized. In order to achieve this purpose, we use the synchronous trigger and the synchronous clock, the internal backplane clock we use to synchronize the clock, and all the modules and the FPGA card are tied together. , Synchronous triggering is provided by the PFI port of 6674T, and the 5783 PLL phase-locked loop is used to lock the signal of 5782 to the Internal Clock PPL ON (IoModSynClock), although the signals generated by the two modules can be locked each time the two modules are run. But the delay of each lock is different. The delay fluctuates between -48ns and 48ns, and the difference is 4ns. I want to keep the delay of each lock unchanged, or make them completely synchronized.
If our function cannot be realized, I hope you can tell me. Thank you for your help.
good luck!
Shuai Shuai Liu
