Digital I/O

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Implementing I2C or SPI with Pxi6508 in Labview

Hi Tom,

Umm, i'm bit confused now.

I'd like to write a data as 01110 ... to a single channel , let's say port0, channel 0( data can be a serial of data, (data array) or it can be only active high or low ) . it can run in continuous samples ( it continues looping back and output data until user stop or call the task stop vi) or finite samples with the clock source control the rate.

So, in labview, I call daqmx do create channel. vi with linetoassign = port0/line0, then with the clock soure, rate and sample mode. However, when i choose vi to write a single channel, multiple samples, i have error on 1D u8 to 1D u32, exept choosing waveform. Same as if i choose single channel, single samples 1 line (error with buffer size), N line (error with # line different # of data )...

That is one the of question I asked "build digital data". Sorry, I'm not familiar with labview yet





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Message 21 of 36

 To ILLG: I want to use as well the AD5290. I want to control it using an USB-DAQ-system. Do you have a working VI to drive the Poti via the digital lines, which I could modify to work with my USB-DAQ? Thanks in advance, Chris 

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Message 22 of 36

I want to implement SPI with my PCI6229 to communicate my microcontroller according to vi which you put in this thread.


However, it is not working.


My microcontroller 's SPI protocol baud rate is 250kbit/s. 


Can you advise me on this problem ?





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Message 23 of 36



I have noticed that many  people need SPI for higher rates with multifunctional DAQ (M series). I had simmilar question, hence I I prepared simple example for you. 


You will find HW timed Master with one implemented mode. You can modify this example to operate as a master in different mode.

How it works? 

1) 8 bit word of MOSI data is prepared.

2) Slave Select (SS) signal has to goes low.

3) Falling edge of SS starts finite pulse train generation on counter (triggered by SS falling edge).

4) Counter output is used as Sample Clock Source for Digital Input / Output (Falling edge / Rising Edge)


I think it is important to note following:

a) SS is SW timed

b) CLK is HW timed


Note that 130 bits of MOSI data is prepared, however just 8 bits is written. This is due to minimum output budder size for digital output buffer.



If you found any mistake of mine, please let me know. (I'm sorry for bit messy code, but hope you can deal with   Smiley Very Happy )




Best regards,



Message 24 of 36

FYI to all, NI Systems Engineering has released libraries for building hardware-timed protocol waveforms that can be generated/acquired using clocked DIO hardware.  The SPI and JTAG libraries can be used with NI-DAQ correlated DIO tasks on any M-series board.  (The I2C library requires open-collector output, which is only supported on the 6534 and 655x.)





Message Edited by David S. on 03-12-2009 05:20 PM
David Staab, CLA
Staff Systems Engineer
National Instruments
Message 25 of 36

Hi David,


As  M series card's digital lines ; like the ones  in 6229 can be configured   to high impedence state (apart from Low and High ) , can SDA  be made tristate before


reading the Acknowledgement bit  so that it can be used as  a bidirectional line ;needed in I2C.Pls let me know ,as i have to use this card for


implementing I2C

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Message 26 of 36



Can you put the SPI code in LV Ver 8.2 as i am not able to open the code which i badly needed to see?

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Message 27 of 36

Hi Jey,

Sorry for inconvenience. Here I attach HTMD documentation.

You can inspire yourself, but I strongly recomend to use solutions David S. posted links to - SPI Digital Waveform Reference Library.



Best regards,



Message 28 of 36

Hi JeyZ -


Someone asked about using the IDW library with a DAQ device over in that thread.  Here is my response to him:

David Staab, CLA
Staff Systems Engineer
National Instruments
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Message 29 of 36

Hi, Tom,


I'm using Labview 7.1. Could you change your code "6508SPIemulation[8.0] " please?





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Message 30 of 36