I am using the Lead-Edge Handshaking Protocol on 6533 board. I am
trying to input data from my device when a rising edge is received
from an external clock wired to my REQ pin. The external clock is a
100kHz 64 pulse finite train. The 100kHz 64 pulse finite train is
being continuously resent at an update rate of 1kHz. I am ignoring the
ACK pulse from the 6533 because my device is programmed to be ready to
send data on the rising edge of the same 100kHz 64 pulse train wired
to my REQ pin. This setup works very well, with the exception that I
am missing data every once in a while (during a 1 hour test I may miss
one bit). I realize that this application is more suited for the
pattern generation with external clock mode. However, because my
dev
ice and the 6533 are communicating via the same REQ pulse...
shouldn't this work all of the time and not miss any bits. Why is the
6533 missing data? If it is because the 6533 is not ready to receive
data... then why isn't ready?
