FlexRIO 6581 Drive Capability

[ds_1]

Hi,

      From the datasheet of the 6851 card, the IO buffer performance should be that of TI SN74LVC8T245. However I'm seeing issues with the drive of this card doing a simple loopback test.

I have the Internal Card Supply 3.3V set up:

 e.g. DDCA Port0 is configured as Write and output port and write a clock out (010101..) on P0.0, I attach the breakout board (NI CB/SCB-2162) to the end of it and I can see the correct clocking data on a scope attached to the breakout board.

If I  have DDCA Port1 configured as Read and read data on P1.1 as soon as I connect P0.0 to P1.1 the clocking data out on P0.0 gets pulled down.

    From a hardware point of view the 6851 signal on P0.0 sees a load of the VHDCI cable in the first condition and the data out is fine with scope on the breakout board pin. Connecting P1.1 doubles this load, (i.e. adding a return through the cable to the 6851 P1) Should this increased oad be enough to pull the signal down?

[SFuller]

Hi,

How are you getting on with this, are you still experiencing this issue?

If so, please can you clarifiy the final part of your post as I didn't completely follow what you were doing and what your question is:

"From a hardware point of view the 6851 signal on P0.0 sees a load of the VHDCI cable in the first condition and the data out is fine with scope on the breakout board pin. Connecting P1.1 doubles this load, (i.e. adding a return through the cable to the 6851 P1) Should this increased oad be enough to pull the signal down?"

If your question is regarding input impedance, I would recommend the following document: http://digital.ni.com/public.nsf/allkb/EAC887B71448E3478625772E0058D7D3?OpenDocument