Reset event counter's current count value using digital trigger ?

[SteveP]

Can an event counter's current count value be reset to zero by an external digital trigger so that it begins counting again from zero ? I have a digital trigger signal at 40 kHz and another digital trigger signal completely asynchronous to it. This second trigger occurs at random times and is not periodic. I need to know when in time each and every of the second triggers occurs with respect to the nearest previous 40 kHz trigger. So the 40 kHz triggger would reset the event counter to zero and then each second trigger occurance would do buffered latch of the current count value. TIO based counter boards such as the PCI-6602 have a Z-index input that KB # 1UGIE1DM mentions being able to do this, but des
cribes position meaurements using encoders as an example.

[gus]

If I understand you right, you need three signals. 1-40kHz signal that resets the counter to zero; 2-asynchronous trigger that latches the current counter value; 3-some sort of a timebase (20MHz or so). This can be accomplished using position measurement. Using the Measure Buffered Position (NI-TIO).vi which ships with NI-DAQ, you can connect signal 1 (reset to zero) signal to the selected counter's default GATE pin (PFI38 for ctr0). Then using the gate specification (scroll left on the front panel) select another PFI for signal 2 (latch signal). Then you can use another counter to generate a 20MHz signal, which you can wire to the SOURCE pin of the selected counter (PFI39 for ctr0). For the encoder specification, select "two pulse encoder". A two pulse encoder coun
ts up on every A edge and down on every B edge. Since B is not connected to anything, the counter will simply count up. Also make sure to enable Z indexing. This should yield the desired measurements.

[SteveP]

Your understanding is correct. I also need to digitize an analog voltage upon each signal 2 occurance (the trigger that latches the curent count). This analog voltage is a 5 usec long pulse (flat top but amplitude varies from pulse-to-pulse). I'm considering using the PCI-6070 card for digitizing. The two data buffers (latched count and analog voltage) read by LabVIEW would need to be correlated. That is, the n'th index of the voltage buffer must correspond to the data in the n'th index of the count buffer. So the analog operation and the counter operations must start at the same time. Can this be accomplished by some synchronized external start method for both of them ?

[SteveP]

Your understanding is correct. I also need to digitize an analog voltage upon each signal 2 occurance (the trigger that latches the curent count). This analog voltage is a 5 usec long pulse (flat top but amplitude varies from pulse-to-pulse). I'm considering using the PCI-6070 card for digitizing using an external scan clock. The two data buffers (latched count and analog voltage) read by LabVIEW would need to be correlated. That is, the n'th index of the voltage buffer must correspond to the data in the n'th index of the count buffer. So the analog operation and the counter operations must start at the same time. Can this be accomplished by some synchronized external start method for both of them ?

[SteveP]

Edited below to add that External Scan Clock using the signal 2 as this clock signal can be used as the trigger to digitize the sample.

[gus]

Yes, you can accomplish this using an external start method for both. Use the "Acquire N Scans ExtScanClk D-Trig.vi" as a basis for the analog measurement and look at the "Generate Pulse Train - Start Trig (NI-TIO).vi". The configuration code for the start trigger can be copied and added into your buffered position measurement example. From here you can choose to either connect the signal to both boards externally or you can use the "Route Signal.vi" to route your start signal through RTSI to each board.

[SteveP]

Using Measure Buffered Position (NI-TIO) example, I am only able to get counter 0 and 1 to serve as the latch signal for signal 2. Only PFI34 (ctr1) or PFI38 (ctr0) work. I've tried changing the counter number to an adjacent gate to this latching gate signal but that did not help.

It appears that the Z Index reset occurs on the negative high-to-low edge. The 6602 manual page 3-19 implied a high level was required. Is there a way to set the edge polarity of the Z Index reset ? Applying the same trigger signal to both Z Index reset and to the Latching Gate causes a count value of zero when the Latching Gate polarity is set to negative. This implies it is a negative Z Index edge that resets the counter.

Is there a way to route an internal timebase (2
0 or 80 MHz) to the SOURCE of the selected counter (PFI 39 for ctr0) being used as the Encoder A input ?