I am trying to use a 6601 counter/timer to count the bits in a high speed serial output from a linear encoder. I've successfully used the counter/timer card to clock and reset the encoder, but I'm having trouble using my third counter input to correctly tell me where the edges of the bit pattern are. I realise I should probably have bought a serial card to do the job properly, but what the heck ;-).
I'm using Borland C++Builder, by the way.
I aimed to use the clock signal to latch the buffer and record a one or a zero in my edge count array to work out whether or not the data signal had changed state.
The signal relationships are thus:
I generate a finite pulse train 24 pulses long at a frequency up to 2MHz on CTR0. This output has a retriggerable start trigger on its CTR0GATE, which is generated at CTR2 (which I have to use instead of CTR1 as CTR1 seems to be affected by what is happening on CTR0 in some way that I do not fully understand).
The CTR0 output is sent to the transducer, which returns a serial bit pattern starting with the most significant bit and ending with the least significant bit. CTR0 is high at idle as this is what the transducer requires to reset to its first bit. If there is no pause at the end of the clock train the encoder returns the same value irrespective of where it actually is (like a sort of sample/hold).
The data return from the transducer comes in on CTR3SOURCE, which uses the CTR0 clock coming in on CTR3GATE to latch the buffer and reload the counter.
CTR2 is a free running infinite pulse train that is usually low but goes high shortly after the end of the pulse train on CTR0 to retrigger CTR0 as described above.
There is some crosstalk on the transducer output from the clock signal, but since I am having trouble reading back the edge count array I can't really tell if it is causing any problems. However, I do know that the linear encoder is behaving as expected.
Thanks for any ideas anyone might have!
Des
