Counter issue error 200305

[Chris S.]

Okay here it goes,

I am trying to output the following variable finite pulse trains out of a counter on my 6071E.  First the period must be able to go up to 100ms and second, I must be able to output this pulse train a fixed number of pulses up to 1500 but doing this gives me a error 200305. 

I assume this is due to the overflow of the counter.  I know that because I am using a 6071E DAQ board, which I believe has 24 bit counters, therefore, I can only do 0.8388608 Seconds of output (2^24 Counter/ 20 MHz Clock Rate) without changing my clock source.  So I tried changing my clock signal to the 100 kHz sample clock, which I believe could give me about 167 Seconds (2^24 Counter/ 100 kHz Clock Rate) perfect. 

Okay that leads me to my problem.  Now I have the time limits I need but I don't have the precision.  By decreasing the clock rate I increased my error.  For instance if I have 1500 pulses at 10 ms PulseWidth by 100ms Period I could have an extra 15ms (or actually like 14.99 ms) of Pulse width in there 1.5% (unacceptable) rather than the 75us (or .0075%) with the 20MHz clock (acceptable).  I can live with anything under 0.1% how would I achieve this?  Can I set the counter that generates the Pulse Width and Period to the 20 MHz clock source and the one that controls the Gating to the 100 kHz clock source?  That way I could have the Pulsing error or .0075% and just .002% Gating error that would give me .0095%.  Is this correct?  Do you have any ideas how I can accomplish this? 

Thanks,

Chris

[Kevin_Price]

Your approach sounds basically right on the mark, but I'm rather puzzled by some of your conclusions.

1. The 100 kHz timebase *can* be used to create pulses with 10 msec On time and 90 msec Off time (for 100 msec period).  And it can be *exact* because the 10 microsec periods of the timebase divide evenly into your integer #'s of millisec.  [Note: exact to within the accuracy specs of the clock itself]

2. The same *could* be accomplished with the 20 MHz timebase, which, as you calculated, can precisely count >800 msec intervals without rollover.

3. As I reread your post again, it sounds as though you're attempting to program the gating yourself.  Are you using the legacy NI-DAQ driver?  The DAQmx driver can take care of some of those messy details for you.  (Note: In the long run, you may be doing yourself a favor by tinkering with and learning about the manual approach which gives greater flexibility for special situations.  But in the short run, DAQmx may get your app doing the right thing sooner.)

4. With manual programming, yes you could use the 20 MHz timebase for pulse train generation while using the 100 kHz timebase for the gating signal.  I believe but would stop just short of guaranteeing that the 100 kHz clock is derived from (and therefore sync'ed to) the 20 MHz clock.

5. Have you actually attempted this yet?  I don't understand your error % calculations, and suspect they aren't valid.  Maybe it depends on the exact frequency you need to generate, and the ability of the 100 kHz clock to divide evenly into the # of pulses you want?

-Kevin P.

[hoffiz]

Hi

There are a couple of knowledge bases I’m going to point you to Unable to Count More Than 167 Seconds with E-Series Device.  Your 6071 E has two counters you can use one of the counters to generate a time base that will go accordingly to your specs, although your resolution will still be controlled by the time base generated. Can you take a look at the example call: “Gen Dig Pulse Train-Finite.vi” a let  me know what you think.

Message Edited by Jaime F on 05-20-2008 01:16 PM

[Chris S.]

Thanks you guys were dead on.

My general idea was correct but my clock error was misguided.  The error is in the clock, not the divider.  I still get the same precision through the 100 kHz clock.  But it would be nice to know how to change the gating and the pulse train counters independently, I can see that being used later on.  I tried to do it with property nodes but to no avail. 

Thanks Guys,

Chris

[hoffiz]

Hi Chris,

I think I’m a little bit confused by your request, “it would be nice to know how to change the gating and the pulse train counters independently”, when you refer to change the gating and the pulse train I guess you mean to change the signal that is going to drive the GATE and the SOURCE, Am I assuming it right?  If I’m not mistaken you question is driven by this previous question: “Can I set the counter that generates the Pulse Width and Period to the 20 MHz clock source and the one that controls the Gating to the 100 kHz clock source?” If you may explain this a little bit more, please.

If that is your case you can’t the gate input of the counter is determined by the type of measurement applications and is controlled by the driver. So pulse generation operates on the principle of TC every time the terminal count is reached the output of the counter toggles. Using the gate for a Finite pulse generation will only make change the number of pulses generated. Generating a Pulse Train with a Counter.

I hope it helps