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Reference Design for Emulating an LVDT Using LabVIEW FPGA

Please post comments, feedback and questions for the Reference Design for Emulating an LVDT Using LabVIEW FPGA in this thread.


authored by
Christian L, CLA
Systems Engineering Manager - Automotive and Transportation
NI - Austin, TX

Message 1 of 8

Hi Christian,

                         I am trying to use the LVDT simulator in FPGA example that you have. I believe the VI's were written in Labview 2015. Can you save it in (convert to) Labview 2012 for me. My setup includes a PXe-8135 RT chassis with a NI 9144 expansion chassis over ETHERCAT.I have been speaking to Rachel Moore at NI & my specific support request number is 7469125.


The zip file on your forum is My email is:




Phone: 310 512 1190

Cell: 310 245 5830

FAX: 310 512 2992


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Message 2 of 8

Hi Harish,


When I designed the code (2 years ago), I put the code in 2013 version. I think the migration process to latest version of LV is automatic (I haven't done anything). That being said, it doesn't answer your question, I know. I'm going to send you a message from my NI email address and see how I can help you.





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Message 3 of 8

Hi Vincent.


I'm still on LV 2014.

Would you please help me with a previous version of your design:




Rainer Langlitz

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Message 4 of 8

Hi Rainer,


Which method are-you interested in, the Simple or Advanced?

What is you use-case? What hardware do you use, what is the frequency of the excitation and accuracy requested?





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Message 5 of 8

Hi Vincent.


I am interestd in the advanced method. My use case is a LVDT simulation with excitation frequency 3 kHz. The other requirements are not clear right now. I would like to run the simulation on a sbRIO. For the design verification I would like to run our code on a lab system to find out what minimum phase shift and accuracy I can reach with a sbRIO. 




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Message 6 of 8

Hi, I am trying to use the project for emulating an LVDT using labview FPGA, I am interested in the simple method, but I need help related to how modify diagrams to have a LVDT with central tap for the secondary windings, the excitation signal I need is a sinusoidal voltage of 7V RMS and 3KHz, a stroke range of 0.420 in


Thanks for your help



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Message 7 of 8

Hi Cesar, 


Have-you looked at the part running on Windows/RT side to compute the scaling factor (used on FPGA)?

At what rate do you need to update the simulated displacement?

What accuracy do you need on simulated displacement?



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Message 8 of 8