D-Type Flip-Flop

[Rico P]

This VI has the Functionality of a D-Type Flip-Flop. Below is the truth table

Clock	D	Q	Qprev
Rising edge	0	0	X
Rising edge	1	1	X
Non-Rising	X	Qprev

The data is only clocked through when the clock input is high but was low on the previous iteration.

The VI is set to "Preallocate clone for each instance" under the execution option in VI properties. This is so if this is used on an FPGA will allocate seperate gates for each instance this is called.