Academic Hardware Products (myDAQ, myRIO)

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digital output myRIO

 

Hi,

 

 

I made a small project using the ExpressVI's of the Digital Outputs of the myRIO.

Everytime I want to execute the program ( send it from my laptop to the myRIO) all the DO's are set. Is there a way to make it standard that all the DO's are false when the myRIO does a start-up?

 

 

thanks

Lars

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When a bitfile is sent to the FPGA, all of the lines are tri-stated. If you want the lines to read false, I would recommend using a pull-down resistor on those lines. That way, when the lines are tri-stated, the DO lines get pulled to a '0'.

 

Best,

Tannerite
National Instruments
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For more specific info check out the myRIO Specifications.

 

On the MXP ports DIO 0-13 have a 40K pull up resistor to 3.3v.  DIO 14 and 15 have 2.2K pull ups resistors to 3.3v.

On the MXP port all DIO lines have a 40K pull down to ground.

 

-Sam K

LabVIEW Hacker

Join / Follow the LabVIEW Hacker Group on google+

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What would the circuit diagram for that look like?

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In your program add a intilize case for Set all the DO states false. So when you run the Code all the DO.s From my RIO Should Be in OFF state

 

LabVIEW Developer

Happy to Wire
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Hi Kristoff,

I want to pull up my MXP port A and B. Can I do it programmatically? if not then what else I can do?

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