Example Code

Inter-cRIO deterministic communications using NI-9469 modules

Code and Documents

Attachment

Overview

The attached code example shows a method for passing fast deterministic data between two cRIO backplanes, making use of a single trigger line on an NI-9469. The example passes data continuously at just under 300kB/s on a single trigger line.

Description

When operating two or more cRIOs together, a common problem is synchronisation. The NI-9469 provides a very nice mechanism to share triggers between chassis over UTP cabling using MLVDS tranceivers similar to those used in ethernet interfaces.

In many applications, synchronisation is often insufficient, and data needs to be shared. In some circumstances, this can be done over the ethernet connection but, in a control system, this is not sufficiently deterministic.

The NI-9469 is far more adaptable than it at first appears. There are effectively 4 triggers lines on the module and you can customise the routing to bring signals in and out of all of these. These trigger lines are not conventional DIO lines. Indeed, all you can do is wait for a trigger event to occur. So the question is, how do we transfer data over this connection. Well, the one thing we can do is vary the time between triggers. These has a minimum of about 40 ticks (1us) between triggers but then, on top of that, we can have a variable delay into which we can encode data. It turns out that the best data throughput is achieved by encoding 4 bits into each trigger time interval. This can be varied and the number of ticks for each code step can be varied but I've found that a 40 tick holdoff and 4 ticks per bit to be the most robust. In fact, with these settings I haven't seen any data corruption in extensive testing.

So we have a transmit VI and a recieve VI. Feed data into the transmit vi using a FIFO and it will immediately transmit it. If it hasn't got anything to do it just sends data one bit too lage to be true data. This allows for re-alignment if the odd and even nibbles are confused at the start.

The recieve VI continuously monitors the inbound data and adds any valid data to a FIFO when it sees it.

Steps to Implement or Execute Code

  1. The example code attached is from my setup, where I have added two 9469 modules into a single chassis for convenience of testing. I have also had it running to custom code on an EtherCAT chassis and also to an EthernetRIO chassis.
  2. Note the configuration of the 9469 modules. You can't interconnect different line numbers in the module but you can modify the routing in or out of the trigx nodes. In this example, just connect a straight ethernet lead between the port0 connectors on the two 9469s.
  3. The FPGA code has two transmit/receive pairs of VIs, one for each module. The first pair takes it's feed from a DMA FIFO and posts back into another. The second pair decodes the data in a receive VI before feeding it across to the transmit VI where it is re-encoded and sent it back again. Basically, we have a loopback on the second module.
  4. The RT code pushes ramp arrays of data into the outbound DMA FIFO to exercise all the possible codes.
  5. The recieved data comes back to the controller, is read off, cut on the last element of the outbound array, and then compared against that original array to detect any faults.
  6. Note. This is just test code and you should manage the loop ending properly and not using the error terminals. (Also, if you do decide to mess with the tick latency and shift inputs, you will probably have to change the tick-timer representation in the subVIs too).

Requirements

Software

LabVIEW 2014

LabVIEW Real-Time module

LabVIEW FPGA module

Hardware

A compactRIO with two NI-9469 modules

Additional Images or Video



Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.

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