FPGA Utilization

[tprohas]

For a FPGA utilization report as follows:

Device utilization summary:

   Number of External IOBs           105 out of 324    32%
      Number of LOCed External IOBs  105 out of 105   100%

   Number of MULT18X18s                9 out of 40     22%
   Number of RAMB16s                   8 out of 40     20%
   Number of SLICEs                 5118 out of 5120   99%

   Number of BUFGMUXs                  1 out of 16      6%

How do I determine how much space is left for additional code?  What is the size of a slice?

[DD]

As you guessed, you are slice limited. The compiler is probably using space
optimization to allow the code to fit. I think I read that this happens
after about 90%. Thus the relationship between size of your block diagram
and the number of slices is non-linear.

[Richard P.]

The FPGA compiler now optimizes for speed, based on testing and on common applications of our users.

Here is a tutorial on reading the compile report:
http://zone.ni.com/devzone/conceptd.nsf/webmain/52c740e80ad2a20986256d6a0055508e


Here is information on changing from speed to area optimization:
http://digital.ni.com/public.nsf/websearch/EE940C191DDCE9CE86256E5500783A4D?OpenDocument

DD makes a great point that the relaitonship is non-linear, as a reesult of the optimization algorithms.

Richard

[tprohas]

Thanks All for the help!

[elmo]

Hello all,

Can anyone direct me to information of reducing utilization (and detailed info about compilation data).  I have a CRIO-9004 with a chassis 9102 and 8 I/O modules.

I seem to be using too many slices and getting errors in compilation (overmapping error code 2).  I am not doing that much in the FPGA vi, except reading writing to the I/O cards and reading PWM/freq signals from the digital input cards.  Since there is no property for detecting edges on this hardware, maybe my logic is requiring extra space.

Thanks

Kev

[UlfN]

---

@elmo wrote:

Hello all,

Can anyone direct me to information of reducing utilization (and detailed info about compilation data).  I have a CRIO-9004 with a chassis 9102 and 8 I/O modules.

I seem to be using too many slices and getting errors in compilation (overmapping error code 2).  I am not doing that much in the FPGA vi, except reading writing to the I/O cards and reading PWM/freq signals from the digital input cards.  Since there is no property for detecting edges on this hardware, maybe my logic is requiring extra space.

Thanks

Kev

---

Here is some tips how to reduce your code size:

- Don't use Divider/Reminder

- Use "Single Cycle Loop"

- Use smallest possible data type; u8 instead of u32

- Avoid arbitration if you can; avoid locals

- Use FPGA memory instead of arrays

- No complex clusters

//Ulf

[Richard P.]

The most common cause of overmapping is too many arrays, and as UlfN mentioned, arbitration can be a problem too. If you use the same VI in multiple places, and it is non-reentrant, then the FPGA must prevent the code from being accessed from multiple places at the same time. To do this, arbitration is put into place, and this is code that takes up real estate on the FPGA.