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TS9650: LabVIEW FPGA: Getting the Most Out of Simulation

by on
‎07-01-2016 03:25 PM
- edited on ‎05-12-2017 09:48 AM by: Community Team

Speaker: Kevin Wenner (AE Specialist, National Instruments)

 

LabVIEW offers several tools to help you simulate your FPGA code. At this session, discover how to take full advantage of these tools to reduce your need for frequent time-intensive compilations. Learn how to include IO stimulus, target/host interaction, and other features to spend more time developing and/or testing code and less time waiting on compilers.

 

*KAW Edit: I just added the presentation PowerPoint for those that are interested!  

Comments
Intaris
Proven Zealot Proven Zealot
Proven Zealot
on
‎08-11-2016 04:57 AM
‎08-11-2016 04:57 AM

Any chance of a PDF or PPT of the presentation for those who couldn't attend?

WishKebab
NI Employee (retired)
on
‎08-11-2016 11:14 AM
‎08-11-2016 11:14 AM

Just updated the OP with the presentation PPT!

Intaris
Proven Zealot Proven Zealot
Proven Zealot
on
‎08-12-2016 10:14 AM
‎08-12-2016 10:14 AM

Hmm, the statement that CLIP IO nodes can't be simulated is not strictly correct as far as I know.  I'm referring to Slide number 44.

 

It's possible to create a template VI for custom handling of inputs and outputs (adding noise, delays and so on).  It's difficult, but it's do-able and I've used it in the past.  It's great for testing.