Undocumented: what is the jitter for digital triggering (NI 4462, PFI0)

[RichardNeiill]

What's the jitter for triggering from a digital input?

If I set the NI 4462 up to sample on a falling edge of PFI0, at 200 kHz, then samples will be spaced 5us apart. There is also a 63-sample delay (315 us).

So...does this mean that my first sample will be measured EXACTLY  315us before the falling edge?  Or is it somewhere from 310..315?  or somewhere from 312.5...317.5?  Or

is the jitter a fraction of the oversampling clock, (so perhaps +/- 40ns ?).

BTW, The NI Dynamic Signal Acquisition docs explain that there is jitter when using analog triggering, but make no mention of it for digital triggering.

Also, if doing reference triggering (i.e. sampling n samples before and m after the trigger), what is the jitter in this case? I'd guess +/- 0.5 sample-periods?

[PHarris]

Hi Richard,

I think the best thing is to check out the Triggering section (starting at Page 2-17) of the DSA Manual which explains all about how the triggering works, but especially the "Triggering and Filter Delay" section.  When you use digital triggering, the ADCs begin generating digital data immediately after receiving the digital trigger signal. However, the analog signal entering the ADCs is still subject to the filter delay. This circumstance means that when the trigger is received, the analog levels at the front of the ADCs are not digitized until a certain number of sample intervals later.. 

We do not specify a delay from when the trigger is received, and when the ADC proces starts, we just say "immediately" as quoted above.  I think this is what you were looking for.

Kind Regards,

[RichardNeiill]

Thanks. I did realise it says "immediately", but in the real-world, there is no such thing!

It might be only half an oversampled clock (i.e. 5us / 128,  which is 39 ns), but it has to exist, both as a delay and an uncertainty.

So I'm wondering what the value is.

[RichardNeiill]

I've just done some measurements on this. To my absolute horror, the jitter is at least 1 whole sample period. The PFI0 "clock" input might as well not exist.

What's actually happening inside this device is that the ADCs are permanently free-running at the specified clock rate. Then the digital "trigger" input just gates whether the next N samples are to be discarded or not.The phase of the ADC sample-clock is totally uncorrelated to the arrival time of the trigger pulse.

The experiment I just did was as follows:

1. Set up a triangle wave (good quality signal generator) at 50 kHz, 0-5V.   Feed this into all 4 inputs (in parallel). Also, use the signal generator's square-wave output to drive PFI0 (in phase with the triangle-wave).

2. Take 20 samples, at 200 kHz, falling-edge-triggered on PFI0.

3. Plot the result, and repeat several times.

What we *ought* to see is a jitter-free, repeatable dataset. (This is exactly the same as setting up an oscilloscope with a square-wave on Ch1, and triangle-wave on Ch2. Set triggering to Ch1, and observe the triangle-wave. The displayed waveform should be stable)

Attached are the results of 3 experimental runs. You may note that the phase is far from constant.

[RonnyJK]

Hello Richard

I have the same effect as you with the NI 4462 PFI0 digital trigger.

Did you resolve that jitter problem?

[RichardNeiill]

Hi. I did resolve the problem, at least to the extent of understanding it. The bad news is, PFI0 does NOT act like an oscilloscope trigger, more like a pulse-counter's gate.

If you ask the NI4462 for 100 samples at 200kHz with a falling-edge trigger, then what happens is this.

* The ADC clock is configured to 200kHz, and they start to free-run at that speed. All samples are discarded.

* The trigger arrives

* The next 100 samples are saved, and returned to you.

My workaround is rather ugly:

1. Extract the 100 MHz master clock from the NI4462 (see other post), by modifying the PCB. Use this as the master clock for everything in your experiment.

2. Configure DAQmx to export the (200 kHz) SampleClock on RTSI6.

3. Operate the 4462 in "reference trigger" mode: this causes the sample-clock to be exported immediately.

4. Sync your circuit with RTSI6.

5. Then PFI0 will "accidentally" have no jitter.