fpga-host data transfer latency performance

[tom_ifms]

This actually closely relates to the post Zynq-7000-performance but I think the issue deserves a seperate title.

I'm working on a control application. So far I've implemented the controller purely on the fpga (in my case PXI7852R). However there are reasons to rather implement it on the host controller (in my case PXIe8108) and just use the fpga to handle the A/D (measurement) and D/A (controller output) along with some signal conditioning. In that case the question is how to get my controller signals from the fpga to the controller and back. As far as I overview things there are two possibilities to do that: DMA FIFO and fpga front panel.

Now, in controls it's the latency of the transfer that matters. I've got the impression that NI rather focuses on maximal throughput instead (what you need in data aquisition).

As Intaris reports in the cited post I first thought DMA FIFO should be the choice. I tested latency and with my hardware I found up to 50 us (fpga to host and back), which is useless for my application. So I did the test also with a handshaking over the fpga front panel and - surprise! - found 4 us. I'm seriously concerned about what will hapen when I implement my controller and will need numerous additional front panel controls for parameters...

How does everybody else implement controller applications with high controller rates?

[RupiDo]

Hi Tom,

thanks for sharing your experience about transferring data between
RT controller and FPGA.

Basically implementation of data transfer depends on your focus of the application.

For high throughput and best resource (logic cells, block RAM, ...) utilization, DMA FIFOs
are used for transfer data.
Because each Frontpanel Element needs a specific number of registers just for storing data.
So the host VI is able to set and retrieve data.


As you mentioned, concerning control applications where is the basic aim is to receive and send
single values as fast as possible frontpanel elements might be the better choice for data transfer.
So as long as enough registers, logic cells are available read/write control transfer via
the frontpanel is definitely an option.

Kind regards,

RupiDo

[alireza_007]

Hi all,

I have the same problem, I do some data aqcusition and filtering in FPGA and I want to send that data to the RT where I Have my controller. I hava to do some mathamtical aprations like (arctan , sqrt ,...) to the signals In RT and then feed them to my control input.  I have 4 signals to send to RT right now ( in final version I will have 20 signals)  . The method I am using to read data from fpga  is "progrmatic front panel commiunication". The problem is, I only can run RT upto 5kHz, otherwise I see the "finished late" message.  I tried to remove chart , graphs and all extra stuff but there was not that much help. Is there a better (faster) way to comumicate between RT and FPGA? 

[p-rose]

Just throwing it out there, when I see trigonometric functions and FPGA in the same sentence I immeditely think lookup table. The trick in these applications is to draw a firm line between what needs to be done quickly (FPGA) and what can be done in RT (relatively slow). I'm interested in seing how others would solve this problem where you absolutely MUST synchronize the FPGA and RT environments and still require extrememly fast loop rates.

[ohiofudu]

Hello Philip,

just as RupiDo said I will use DMA FIFO for data transfer from FPGA to Host.