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Writing multiple elements to a FPGA to RT DMA FIFO

Hi,

 

I have a small issue. In my current acquisition application I am able to acquire data at 1 MS/s and timestamp each sample successively at microseconds. I am using DMA interleaving on the FPGA and am successfully able to reconstruct them on the cRIO.

 

Now , here lies the issue I added some processing steps on the FPGA to discard some unwanted data before transmitting it to the cRIO, now  if I use DMA interleaving technique to transfer necessary data with the corresponding timestamps , there is unexplained channel switching after I use the decimate 1 D array function on the cRIO.

 

I have used the following FIFO  configuration settings.

 

1:I am using 3 DMA channels with a DMA size of 32 elements(i.e. I am using write multiple elements at a time) so at a time I am writting thirty two elements onto the FIFO after I acquire a valid data of total 32 elements, so I have to wait for some time till I obtain this valid data chunk of 32 elements onto the FPGA .I later write it together on the FPGA to RT DMA FIFO.So I have accordingly set the FIFO Timeout to a very large value on the FPGA.

 

2:On the cRIO the Requested FIFO depth is set to 32*3*10000, which is fairly large, also based on several discussion posts I have also checked the number of elements remaining in the RT FIFO , if they are greater than or equal to 96000, then I read the 96000 elements, which is also a large data chunk.

 

3:I am also continously  monitoring the number of elements remaining in the FIFO on RT  and they never exceed the FIFO depth, yet I am encountering the channel switching.

 

I tried several debugging procedures . However, I have no clue why this is happenning. It would be great if anyone could share their inpputs on this.

 

Thanks.

 

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It would help your cause if you could post at least a stripped down version of your code.  You likely have a bug in there that another set of eyes could help to find.


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Hi,

 

Please find attached the section of code on the RT.

 

I apologize for not being able to post the latest version of the code on RT. The below snapshot has only one change. The Requested number of elements is not 90000 , but 960000 and the Total Number Of Elements remaining is 96000, in the current case and not 90000 as in the snapshot.

 

Thanks once again.

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Where is the interleaving?  And shouldn't you be reading an number of elements divisible by 32 instead of everything that is in the FIFO?


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Unofficial Forum Rules and Guidelines
"Not that we are sufficient in ourselves to claim anything as coming from us, but our sufficiency is from God" - 2 Corinthians 3:5
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Hi,

 

I am setting the number of elements as 96000(Done this in my latest version . However, this detail is missing in the current snapshot), I check in the Case Structure on the RT if the number of elements are greater than or equal to 96000, inside the True Section of the Case Structure I wire 96000 to number of elements of the FPGA to RT FIFO Read. I guess this allows me to read elements which are divisible by 32. I am not sure if this is the correct way of checking if the number of elements are divisible by 32.

 

I am using DMA interleaving in the sense that in the same FPGA to RT DMA FIFO I am transporting all the sample values as well as the 64 bit Timestamps.

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Hi,

In order to Summarize . I have set the Number of Elements to Write as 32 in the FIFO Configuration pop up window and since I am using three DMA channels and each channel is fed with a Fixed Array Size of 32 elements so I set up the FIFO depth on the RT as well as the Case Structure part of the implementation to an integer multiple of 32*3 (i.e. 32*3*10000=960000).

 

Thanks.

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Hi Hars,

 

This is normally an indication that you are getting an overflow, can you try adding another monitor? Where you OR the timeout flags, add a latch on that value (OR it with the previous value). It maybe timing out but so quickly you don't see the flag go high.

 

Also do this on the local FIFO, perhaps this is timing out and not the host FIFO.

 

I'm trying to understand the FIFO setup better. So are the 3 FIFO blocks just 3 DMA FIFOs with the same name? It looks like the same from here.

 

On the face of it I don't understand using the 32 elements. This would make sense where you have multiple channels but it looks like each FIFO is just using 1 channel (1 for time, 1 for data) so you may be making life harder rather than letting LabVIEW manage optimising transferring the data.

 

I would also be tempted to create another loop for the data transfer so you separate the IO node section from the data transfer. This reduces the risk that these two elements are messing with each others timing and may make some problems clearer.

James Mc
========
CLA and cRIO Fanatic
My writings on LabVIEW Development are at devs.wiresmithtech.com
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Hi James,

 

Thanks a lot for your elaborate explanation.

 

1:I have still not used the latch for determining the Time Out and I would definetly use the shift register to latch the data and check if any of the FPGA to RT FIFO or the Local FIFO is timing out tomorrow.

 

2:The Three DMA FIFO's are the same FPGA to RT DMA FIFO. What I do here is I fee dthe first FIFO with the sample values and the unsigned 64 bit timestamp is split into  two 32 bits so I am feeding the second FPGA to RT DMA FIFO with the first 32 bit of the timestamp value and the second FPGA to RT DMA FIFO with the second thirty two bits of the timestamp value.

 

So its basically,

 

64 = 32(First FPGA to RT DMA FIFO) +32 (Second FPGA to RT DMA FIFO)

 

I intend to process the relevant data before filling in the FPGA to RT DMA FIFO so after processing I build an array with the series of valid data points which need to be transmitted to the cRIO . Hence, I collect say 25 valid data points now I need to feed them along with their relevant timestamps onto the FPGA to RT DMA FIFO , so in order to write them at once . I set the Number of Elements to Write in the FIFO Configuration pop up box to 32 , because its the maximum number of elements I can write at ont time. I am not sure if using this kind of a setting is causing the issue.

 

I write these valid data points simultaneously in all three FPGA to RT DMA FIFO's.

 

I did  not quite get the last point of seperating the I/O node section from the data transfer . Could you please eleborate on it?

 

Thanks once again.

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Hi,

 

Ah that makes more sense. What you have described means it is very likely you will find there is a timeout occuring on one of the FIFO calls. See what the latch values give you.

 

The separation bit would be to have a loop that just reads the AI and timestamp together and then sends them in a FIFO together to another loop who's sole job is to get this data to the host. That tends to give some more flexibility in how it might work. It also means that right now you could miss samples if your write to FIFO code takes longer than 1us since it is in the same loop as reading the result of the 9223 conversion.

 

Cheers,

James

James Mc
========
CLA and cRIO Fanatic
My writings on LabVIEW Development are at devs.wiresmithtech.com
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Hi,

 

I finally latched the Time Out and observed that it does not actually Time Out. I further had a look at the FPGA VI and somehow feel that the issue could be in the way in which the elements are read from the FIFO on the cRIO . I actually write 32 elements at a time in the FPGA to RT DMA FIFO on the FPGA. While reading the elements from the FIFO I use a Decimate 1D Array function . I doubt if this could cause an issue as the first FIFO on the FPGA contains an array of 32 elements of the sample values , the second FIFO contains the first 32 bits of the unsigned 64 bit timestamp and the number of elements are 32 here(when written for the first time) , the last FIFO contains the last 32 bits of the unsigned 64 bit timestamp and the number of elements written in the FIFO at the same time also equals 32((when written for the first time). I really do not know exactly if decimate 1D array(in Host.png snapshot) could actually return appropriate values on the cRIO . I think this could be the probable cause of channel switching. I would really welcome your inputs on this which would help me understand if my observations could be correct.

 

Another thing is if I wrote single elements into the FIFO when I attempted signal acquisition and timestamping without processing , things worked out  fine

 

Thanks.

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