Triggered Data Acquisition using FPGA

[lfw]

Hi all,

I am trying to read the digital data from my ADC (12 Bits, Parallel) using FPGA (PXI-7833R). The digital data is only ready at the digital output ports of the ADC at the falling edge of another digital port from the ADC, hence the vi will only read the digital data from the ports when it detect a falling edge. The data is then passed onto the Host VI using DMA.

I have actually wanted to have control on the amount of data I collect, so I designed the fpga VI to stop after detecting a preset amount of falling edge. However, I have the problem of having more data in more FIFO than expected. For example, when I preset the FPGA VI to stop after detecting 500 falling edge, I will have more than 500 data values in the file which i saved in the host vi.

I believed it is a timing problem such that the digital data may be captured more than once per trigger of the falling edge. Can anyone advise on how I can solve this problem. Attached is the .lvproj, host vi and fpga vi.

Thanks.

Regards,

Fw

[CharlieM]

Fw,

Your logic in the FPGA VI looks good. The only reason I would expect to see more data in the buffer than the preset amount is if there was leftover data. You should use a FIFO Clear every time the VI starts and every time the reset is pressed.