Timed Loop Clock wire bug (FPGA only?)

[Intaris]

When a SCTL has a clock connected via wire, it appears that it cannot be renamed. The Configuration Dialog allows it, but next time you open the dialog, the old name is still there.

This occurred to me during a search for a bug which I unfortunately cannot reproduce.

I don't think this inability to rename is intended behaviour.

[Jacobson-ni]

Just a question but what does naming the loop do for FPGA?

I know for non-FPGA systems you can control loops by names and I believe that name is also used for the thread name but I've never thought of changing them on FPGA. My best guess is that generated VHDL names are based on that but I don't really know.

[Intaris]

I would also assume that the VHDL names are based on the SCTL names.

It's problematic allowing a user to change settings without actually changing them.  I don't know if it's possible to find specific SCTLs based on name via scripting, but if I would go through my code "renaming" the loops to allow me to locate specific instances via scripting and then find out that it's not working, that could lead to some weird situations.  Nothing about the user interaction with the SCTL dialog hints at the operation not working.  If the name of the SCTL would always be visible, then it might be apparent, but nearly all of my loops do not show the actual name.

It's not a huge bug. It's a niggling one. But it's the kind of bug which leads to searching for errors in the wrong place, and that can be very costly in terms of my time.