09-12-2005 01:46 PM
Re: Timed Loops -- yeah, I think your output buffer would need to contain multiple waveform cycles. And I could imagine some noticeable CPU time inside the timed loop to write those tens of kilo-samples to the output buffer, though I don't think the algorithm gets much more complicated. I don't think the FFT's would co-opt the CPU and slow down the timed loop, but the timed loop may starve the CPU enough that the FFT's themselves bog way down. And I'm not sure how timed loop scheduling interacts with DAQ calls. Like you said, all the processing required for this timed loop solution does feel like a big price to pay. If I were you I I think I'd also waste 2 AI channels to measure my AO.
Other annoyances where NI's DAQ drivers fail to provide a reasonable symmetry from input to output: First and foremost, why can't I take a TTL waveform I measure in semi-periods with a counter and then recreate it on another counter? Why don't counters have any buffered output capability? This also becomes a gripe with timed DIO. One of the touted features is "change detection" and you can, with some pain, set up change detection with another board's counter capturing timestamps whenever a bit changes while the DIO buffer captures the DIO port at the change instant. Kinda cool, until you realize that without hw-timed counter output, you can't use that measurement data to reproduce this digital timing pattern as an output stimulus. By comparison, the board & driver put out by Viewpoint Systems (one of NI's Alliance Partners, no affiliation with me) has a completely symmetric driver for input and output that simply makes a ton of sense.
-Kevin P.
09-12-2005 01:51 PM
09-20-2005 09:00 AM