FPGA compilation problem

[sbailey64]

I developed some FPGA code under "Labview 2009 Service Pack 1" for the CompactRIO. I have been using this code successfully for the past 1.5 years. I just installed "Labview 2011"  and suddenly this code will not compile. I get the following error message:

"LabVIEW FPGA:  The compilation failed due to timing violations, but there is no path information because the timing violations are not of type PERIOD."

Any ideas?

Thanks,

Steve

[Blayne_K]

Hello Steve,

There have been some reported issues related to resource usage and timing issues depending on the Xilinx tools being installed alongside Labview FPGA. To better isolate what might be at play here could you please list your cRIO Chassis and your Xilinx tools installed. 

Best,

Blayne

[sbailey64]

Hi,

We are using the cRIO-9114 chasis. As far as Xilinx tools, there we two directories under the C:\NIFPGA\programs directory. They are:

Xilinx10_1 and Xilinx12_4

In these directories, exist all manner of files and programs that Labview probably calls. Since I (the user) don't have direct assess to these tools, I am not sure what is installed.Can you direct me a little more for detail you want?

Steve

[Blayne_K]

Hi sbailey64,

I did some searching to see if the timing failure could be related to your specific hardware and the Xilinx tools upgrade, however I wasn't able to come up with anything along those lines. Considering that you just started witnessing this timing violation subsequent to upgrading to 2011 (assuming no changes were made in your VIs), the most likely root cause of this is due to the compiler changes that were intended for optimization purposes in that version alongside the changes in Xilinx tools as well. I would suggest the best way to eliminate these timing violations would be to pipeline as much as possible throughout your code where you have single cycle time loops. If you haven't yet explored much related to pipelining a good place to first look is: http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/fpga_pipelining/ .

Best,

Blayne

[msiegl]

Hello,

I am receiving the same error message in a very similar scenario (upgrade to Labview 2011) - were you able to resolve your issue and if so how?

Thanks a ton!

[sbailey64]

Blayne,

My FPGA code is already optimized using pipelining. This is a bug on the part of NI and/or Xilinx and needs to be fixed. Putting the burden of this bug on the customer is not an acceptable solution. I spent months optimizing and making this FPGA code work to now find it is broken with 'upgraded' software. Please advise.

Steve

[Donovan_B]

Steve,

Is there any way to get an example of the code that is failing.  You are right, this particular violation indicates something in the compile chain and not necessarily something on the LV FPGA diagram.  However, without having some idea of where the violation is occurring, we can't really advise you on what is happening.

[sbailey64]

Hi Donovan,

Sorry for the delay, but it took me some time to boil my FPGA code down to one Vi. I  have included the vi in question along with the project file. Do realize I am pushing the CompactRIO to its limits as I have defined a 200Mhz SCTL. I tweaked this code using "Labview 2009 Service Pack 1" and it compiled and worked beautifully for the past year and a half. Under "Labview 2011 DS2", compliation fails with a timing violation. I need the 5ns period for my counters.

Regards,

Steve

[WHoebel]

Hallo!

Same Problem here. Compiling on LV 2010 everything is fine. Change to LV 2011 result in error described above. Switch back to LV 2010 and the error does not appear again.

cRIO 9073

The problem comes up with implementing CANopen features in the FPGA.

Xilinx Log Attached

[srm@viewpointusa.com]

we have also observed problems with 2011 that did not exist in earlier versions.  NI is still looking at the issues.  we will not be moving to 2011 until they are resolved.