[FPGA] Reduce the number of DSP48s

[gerardpc]

I'm having trouble reducing the number of DPS48s in the vi of the attached picture. Changing the compilation strategy to "Area" optimization doesn't apparently change the number DSP48s used, which as can be seen in the other picture is my resource bottleneck (I have plenty of other resources to use). I imagine that sine wave generators are to blame, but I'm not completely sure, and I don't know if anything can be done about that.

[dan_u]

A very simple thing would be to replace the *2 with a simple bitshift. Just shift your FXP number up 1 bit, which is a free operation on the FPGA and does not utilize any resources (and also no time).

From the screenshot we can't see your FXP configurations, maybe you could reduce DSP48 usage by decreasing the number of bits (e.g. if the DSP48 on your target have 25x18 multipliers and you multiply 2 32 bit numbers you'll use 4 DSPs, whereas multiplying a 25 bit number with a 32 bit number uses only 2).