FPGA - 2 parallel code chunks are acting strange

[Dvido]

Hi,

I'm having a strange problem with my FPGA code. I'm using a 7852R board with a PC. My goal is to simultaneously sample 2 Analog Inputs (AI), delay them by the same number of clocks, then perform some simple mathematical actions between each one of them and a file read from the PC (using a DMA FIFO) and then transmit them to 2 Analog Outputs (AO). I've divided the code into 2 "courses", both of them are completely identical - AI -> delay -> interaction with file read from PC -> AO.

The strange thing is that they're not acting in the same way - actually what I see is that the change of the delay value impacts only one of them while the other one remains as it was. Per my understanding the analog output signals are supposed to be identical. As you can see in my code, I've wired the Timeout outputs of different FIFOs to DIOs for debug purposes - I can see that DIO14 isn't toggling at all while DIO7 (which is supposed to be completely identical) is working fine (toggling at the rate set by the host),

Please help me to understand what is wrong and how can I fix it - it is very urgent.

Also, I would appreciate some thorough explanation regarding the behavior of a FIFO (couldn't find any in the website) - for example: The behavior of the Timeout indicator, what happens if an element is read from a FIFO into an empty "thing" (like a "case") etc.

My code is attached.

Thanks in advance.

[charris]

Dvido:

That seems like a lot of code to simply pass 2 analog inputs through some processing and back to the analog outputs.

You might want to start by consolidating your code into fewer while loops. I'd recommend starting with a blank FPGA VI. Add a while loop, and read the two channels inside of it. You can pass those channel values to the math/analysis functions you want to perform. Once that's done, pass the data through a target to host FIFO to send it to the computer, and also pass the values to the analog output nodes.

For detailed information on the behavior (esp. timeouts), I'd recommend the documentation here:

FPGA: FIFO Read and Write method details

Host: FIFO Read and Write method details

If you read a FIFO element to an empty "thing," it will still read the value from the FIFO (removing it from the FIFO). What happens after the FIFO will follow standard LabVIEW dataflow rules. If the data is wired to a node but never used, the node will just be overwritten each time it's executed. It will still pull data from the FIFO.

[Dvido]

Hi Caleb,

I modified my code in many different ways, I also tried to simplify it but still I see that the "Right" part is not the same as the "Left" part. The reason that the code seems big is that I split it after I first saw that phenomena because I though that it would fix it. If I would wrote that code using  a proper VHDL coding, 2 different and independent identical code pieces would behave in the exact same way. For some reason they aren't the same when I use LabView.  Please advice how can I debug and fix that.

About the FIFO: You said: "you read a FIFO element to an empty "thing," it will still read the value from the FIFO (removing it from the FIFO). What happens after the FIFO will follow standard LabVIEW dataflow rules. If the data is wired to a node but never used, the node will just be overwritten each time it's executed. It will still pull data from the FIFO."

Unfortunately I disagree, at least according to what I see in my code. As you can see, I have combinations of different FIFOs in a single loop (i.e.. for summing or multiplying). Each of these operations is performed in a "case" structure while the case True/False condition is defined by one of the FIFOs. Obviously since the FIFOs aren't synchronized, the samples are pushed into the FIFOs in different times and yet the operations are performed OK (I can see that with a scope on the AO) - please explain that.

Thank you

[Ben_J1]

Dvido,

   Can you upload your modified code? Also when I load it up none of the front panel objects are initialized to a meaningful default value. Can you set the default values by right click on them and going to Data Operations >> Make Current Value Default so I can see how the timing plays into things?

Regards from Austin,