FPGA Design Pattern - Four Wire Handshake - N Input to M Output

[RVines]

Overview
This tutorial extends upon Daniel's post which is a four wire handshake tutorial

Description

The purpose of the four wire handshake method is to parallelize many tasks. This is very useful when you have tight timing requirements. If your current code has a critical path timing dependency causing the compiler to fault out then you either need to remove, simplify, or parallelize your code to meet your SCTL loop constraints. The four wire handshake is a great method that inherently forces parallelization. 
Requirements

• LabVIEW 2012 (or compatible)

Steps to Implement or Execute Code

1. Unzip " 4 Wire 2012 NIVerified.zip"
2. Implement the programs inside in your project

Additional Information or References

Drawbacks and Use Cases

This N Input to M Output design pattern “instantly pauses” when the downstream VI is not ready for data. It could be modified to “pause” only after the next valid output. As such, it should not be used if your function falls into the original 1 Input to 1 Output over N cycles case. You will likely get better throughput as the original design will allow the parallel sets of code to continue to run until they produce a valid output.

 **This document has been updated to meet the current required format for the NI Code Exchange.**

[heel]

Thanks RVines,

This is good stuff - works great - saved me days of work!

[heel]

This code on custom module with 4 wire handshake design - should be in the Examples collection in the LV installation in some form or another,

There are many examples there on how to use the standard blocks like fifo's and high speed math but none for how to build custom blocks. And 4 wire handshake is really difficult to get right - the back pressure part is the sneaky one.