digital clock reset problem with 74193N

[Cqiao13]

Hi, i'm designing a digital clock circuit.

However, i faced problems during reset part.

when i tried to reset on 3(U11) with 1 NAND gate and 2 NOR gates,
i think i don't make mistake to reset with 0011(U3),how come the 3 will also appear on the seven-segment display?

Well,i also wonder how can i reset  the other seven-segment display(U9) to show the following sequences:
0,1,2,3,4,5,6,7,8,9,0,1,2,3,0,1,2,3,4,5,6,7,8,9,0,1,2,3,0.. 

Lastly, is that possible to configure the transmition speed in multisim 11.0?
 
Thanks.. 

[Tayyab_R]

Hi,

There were a few problems with the circuit which is why the clock was not reseting at 3. I have modified the file. Please take a look and see. You will need to add a buffer between the second input and the AND gate because otherwise, the gate will trigger before the output has actually reached the desired state.

I had to edit the delay time in the buffer to make it work of this circuit. To edit the delay time, double-click the Buffer and under the Value tab, click on Edit Model. You can change the rise time and fall time from this window.

Hope this helps.