Question about myRio Hardware (ADC/DAC)

[Anton.S]

Hi!

I'm interested in new myRIO product. But there is one unclear question:

What is the ADC-DAC responce time on myRio platform ?

I mean experiment like this:
ext signal (meander) -> (ADC-myRIO-DAC) -> ext scope chan1
ext signal (meander) -> ext scope chan2

What's the difference (ms/us)?
Is it a constant value?

I found (USER GUIDE AND SPECIFICATIONS
NI myRIO-1900) that ADC is 500Ksps capable and DAC is 345Ksps capable.

Does it mean that 1/500K+1/345K responce time is achievable ?

Is ADC/DAC connected to PS (Processor Subsystem) or PL (Programing Logic) parts of Zynq IC in myRIO ?
I can little explain what I mean:

PL part is FPGA fabric and ADC-DAC transformation has relatively small constant time,

PS is ARM core and ADC-DAC transformation has undetermined delay because of OS/interrupts/etc.

thanks a lot!

[Craig_]

I think that all of our RIO platform directely connects all user accessible IO pins to the FPGA.

If you architect the FPGA loop properly you should be able to read in the AI, do some processing, pass the result into a feedback node, and connect the output of the feedback node into the AO at up to 345KS/s.

The overall responce time in this case would be 345K * 2 based on the rate limit of the AO vs the AI.

[Kristoff2]

The myRIO hardware block diagram is here: http://zone.ni.com/reference/en-XX/help/373925A-01/myriohelp/myrio_hardware_bd/

I think you are correct that (approximatly) 1/500K+1/345K response time is achievable.  There will be an extra FPGA clock cycle or two but that should be insignificant compared to the ADC and DAC rates.

Let us know if that answers your questions.

Thanks!

-Sam K

LabVIEW Hacker

Join / Follow the LabVIEW Hacker Group on google+

[toshas]

Hi!

Thanks for sharing hardware block diagram!

Only one question still exist for me:
How SPI buses are routed ? Is it individual bus for each ADC/DAC ? Or is it one bus for ADC and another for DAC ? Or something else ?

This is important too. Because we take into account not only responce time but also overal throughput.

In case of independent buses we can achive this:
Frame1 (1/345K) (Read ADC and Write DAC)
Frame2 (1/345K) (Read ADC and Write DAC)
Frame3 (1/345K) (Read ADC and Write DAC)
on every ADC/DAC pair!

In case of shared bus:
Frame1 (1/500K) (Read ADC)
Frame2 (1/345K) (Write DAC)
only for 1 channel.

I found (NI myRIO-1900 User Guide page 8 (Analog Output Channels)) such description
"MXP connectors A and B share one bus, and MSP
connector C and the audio outputs share a second bus."
This description isn't clear for me. Is it about all SPI buses (ADC and DAC) or just for DAC ?

thanks a lot!

[Kristoff2]

The stated rates of 345K and 500K should be independent and take into account the ADC / DAC sample, setup and hold times, SPI bus, etc.  I'll see if I can find more specifics on the HW side.

-Sam K

LabVIEW Hacker

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[Kristoff2]

Hey,

For this question the best way to think about the myRIO hardware is as if it has two ports the MSP and MXP (don't distinguish between A and B on the MXP connectors).

The MSP AI, MXP AI, and Audio In (ie all the AI) share the same ADC.

The MSP AO and Audio Out each have their own DAC but share an SPI line.

The MXP AO has its own DAC and has its own SPI line

I tested the delay you were asking about by connecting AI0 to AO0 in the FPGA.  The delay between the source and the output signal was about 7 uS and when you include the skew of the output signal about 15-20 uS between the signals.

-Sam K

LabVIEW Hacker

Join / Follow the LabVIEW Hacker Group on google+

[toshas]

Hi!

Thanks a lot!

This is exactly what I wanted to know.

[Kristoff2]

Happy to help!

-Sam K

LabVIEW Hacker

Join / Follow the LabVIEW Hacker Group on google+

[Anton.S]

Hi!

Could you help me once again. I got some strange behaviour during above task implementation.

First of all I measured AI and AO time with attached snippet's. I got respectively 2 us (500 KSps) and 2.8 us (350 KSps). And this is absolutely ok.

[Anton.S]

Then I connected AI to AO inside one Loop in sequence manner.

And I got 4 us time which is smaller (about 1 us) than expected (2 us + 2.8 us  = 5 us).

What kind of optimizations was performed ? It is a little bit strange time.

ADC-DAC-seq-1 picture represents signal transfer through myRio.