Changing the "Open FPGA VI Reference" Timeout

[dwisti]

I'm connecting to a cRIO-9101 FPGA from a host PC.  If the cRIO is not avilable, Open FPGA VI Reference takes 20 seconds to timeout.  How can I specificy a different timeout?  I tried using a VISA timeout property node but it returns an error.  The Open FPGA VI Refernece function is set to "Show Resource Input" and the resource name is visa://192.168.xxx.xxx/RIO0::INSTR.

[JMota]

Hi dwisti,

Unfortunately, there is no way for you to specify a different timeout. Using the VISA timeout property is not going to work because the timeout is from the Open FPGA Reference node attempting to open a session to the remote target. I can think of a couple ways you can workaround this:

1. Use the RT Ping Controllers or the Open TCP Connection VIs to make sure the device you are contacting is on the network before you do an Open FPGA Reference. You can specify a custom timeout for those VIs, so you would not have to wait the entire 20sec before figuring out the controller is not accessible.

2. Open a VISA Session with a custom timeout. If it succeeds, then close the reference and proceed with the Open FPGA Reference. If it times-out, then no need to execute the Open FPGA Reference code.

Hope this helps. If you feel it is important for the Open FPGA Reference to let users specify a custom timeout, please describe your use case so we can create a suggestion for R&D to look at.

JMota
National Instruments

[dwisti]

There is good reason for a custom Open FPGA VI Reference timeout.  I tried your suggestion to open a VISA session with a custom timeout. The VISA session still did not work and waited approx. 20 seconds to timeout.  FPGA read and FPGA write also have a 20 second timeout, you really don't want to ping or open a VISA session every time you read or write to the FPGA.  Again, a custom FPGA timeout would be nice.  Close FPGA VI Reference has a 2 minute timeout! In 99% of FPGA applications, a timeout is not needed because the FPGA hardware is directly connected to the host, (i.e cRIO) however in my case my host application is a PC connecting to the FPGA over Ethernet.  Therefore, the need for custom timeouts become more evident.

[Doug M]

dwisti,

I filed a product suggestion to the LabVIEW FPGA R&D team for allowing the user to specify a custom timeout value for the Open FPGA Reference VI. 

However, I am a little confused as to why JMota's idea of opening a VISA session to your FPGA device doesn't work.  This should work.  I tried it with a cRIO backplane and it worked fine -- you may want to make sure the version of NI VISA on your remote target is the same as the host, that the remote target has both VISA and VISA Server installed, and that it has permissions set for your host to open a VISA session to it.