F-gen Scope Tclk synch

[Brett_J]

Hi,

I have a PXI 5922 and a PXI 5412. I am trying to synchronise the cards using the tclk functions provided.

I have set the 5412 to receive an external trigger on PFI 0. Then used Tclk in an attempt to start the digitiser at the same time.

The problem I am having is that the digitiser is missing data generated by the f-gen. I know this particular f-gen has a delay of 43 samples + 110ns before it starts generating a waveform, but does this delay also apply to starting the PXI-5922. Using a scope there is an approximate delay of 120us.

I have also tried the other way around, where I have set the digitiser to recieve the external trigger and then configured the tclk. The f-gen starts instantly and the digitiser waits for the trigger before starting. 

Hopefully there is something simple I am missing. Any suggestions would be greatly appreciated.

Regards,

Brett 

[Brett_J]

When running the other way around with the 5922 receiving the external trigger, the 5922 acquires but does not receive any of the waveform generated by the 5412.

Cheers,

Brett 

[Jordan F]

Hi,

Try out this example on our website to see if you can get the two synchronized without missing any samples  (im not sure if you have already tried this example or not).  I know it does not use an external trigger but you can modify the code to add this in.  Also, since you are using Tclk, the FGEN and digitizer should be synchronized and the delay should be accounted for then the program is run. 

NI-TCLK Synchronize AWG and High-Speed Digitizer

http://zone.ni.com/devzone/cda/epd/p/id/5029

[Brett_J]

Hi Jordan,

If I externally trigger one of the devices, will Tclk trigger the other device for me? Does it matter what type of signal I use, digital or analogue?

Cheers,

Brett. 

Message Edited by beej on 01-30-2009 11:10 AM

[Jordan F]

Yes, you will need to route the external trigger to your master device (not all devices) and then Tclk synchronize the two boards in the backplane.  Here is a good article on how Tclk works.

National Instruments T-Clock Technology for Timing and Synchronization of Modular Instruments

http://zone.ni.com/devzone/cda/tut/p/id/3675

As far as the difference between analog and digital triggers, the performance should be similar but depending on the device you might see a faster trigger when using an analog.  This is something that you can test out in your system.

[Brett_J]

Hi Jordan,

I managed to get the example working

Is there a way to ensure I get the start of the fgen data?

When I try to use the digitizer as the trigger, it misses the f-gen data, but I believe this is because it is not being recognised as the master device. How do I ensure the device I am triggering is the master, is it purely based on the data flow due to the error wires?

Cheers,

Brett 

Message Edited by beej on 02-03-2009 11:47 AM

[Jordan F · Accepted solution]

I am glad you were able to get the example working!  I am curious as to how you are checking that data is being missed by the digitizer.  How many samples are missed and what is the current synchronization you are getting?  You can try setting the scope as the master device and receive the external trigger but you might need to modify the code to account for this (switch the two tasks in the program).  The device that is receiving the external trigger is considered the master device. 

The advantage of using Tclk when synchronizing is to have devices respond to triggers at the same time (on the same sample period) and have very close alignment of the sample clocks.  The device that receives the  trigger from an external source or generates it internally will send the signal to all devices, including itself, on a falling edge of TClk.  Tclk enables accurate triggering of the synchronized devices with a skew of around 200 to 500 ps.

[Brett_J]

Hi Jordan, 

The reason I believe data is missing is because the sine wave I am generating with a zero phase offset is read with approx 4 degree phase offset (pretty constant). I have also noticed that the delay in generation after triggering has gone from 80-82us (no Tclk) for a 500kHz to between 500-1050us (using Tclk) for the same 500kHz waveform (measured on a cro). Is there a reason for this or any way to reduce the generation delay?

Also when the external trigger is sent to the scope and I switch the two tasks in the program, the scope captures some of the waveform but with a phase offset that differs constantly.

The goal of the application is to generate a waveform on a fgen, read it with a scop with a 1-2 clock cycles of data missing at most, and a constant delay between trigger and generation. The 43 sample clock periods + 110ns delay is acceptable. Also required is a constant phase offset. Is there a better way to do this or is Tclk the best option?

Cheers,

Brett 

Message Edited by beej on 02-05-2009 09:19 AM

[Jordan F]

There will be a delay in generation when using Tclk because Tclk has to synchronize the triggers on a rising or falling edge of the clock.  So, there will be some delay because all the devices will not receive the triggers at the exact same time and Tclk will not start generating or aquiring until all the triggers are received.  Tclk is definitely the best way to synchronize your two devices because of the ease of setup and the synchronization of triggers when starting the task.

Also, there are different factors that affect the phase offset such as the cable length you are using from the FGEN to the SCOPE.  How do you currently have it setup and how are you measuring the offset and delay?

[Brett_J]

Hi Jordan,

The phase delay is not an issue, rather the phase jitter. It is being measured using the tone measurement VI and also by multiplying the generation waveform with the acquired waveform, then applying a LPF. This is being done on multiple runs and the phase offset is being compared between the runs to determine how much it changes. With Tclk the phase jitter we are measuring is acceptable, but we have an unknown and long start delay.

The start delay is being measured with a CRO, the CRO is recording from the external trigger until it recieves output from the FGEN. As I mentioned the delay is too long when using Tclk. Without Tclk there is a delay of only the 43 sample clock periods + 110 ns (84us with a 500kHz waveform), but the phase jitter is too varied.

Is there something I could implement to keep the phase jitter down and the delay down or to a known length?

Thanks,

Brett