simple (?) problem using DMA-FIFO host to target

[ferring]

Hello,

I have a problem using a DMA-FIFO "host to target" to transfer data to a FPGA.

If I simulate the target vi on a dev computer, the FIFO works fine (I push an array on the host vi and can pull the elements one after another). But if I run the target vi on the FPGA-target, I only get the first element.

Thanks in advance.

[Marco_Brauner]

Hello, 

can you please check out this example coming with LV FPGA:

C:\Programme\National Instruments\LabVIEW 2009\examples\

CompactRIO\FPGA Fundamentals\FIFOs\FIFO Communication between Loops\FIFO Communication between Loops - cRIO.lvproj 

regards

M. Brauner NIG 

[Citra]

Hi Ferring,

How did you resolve this issue? I'm facing a similar one.

I'm writing an array of elements from the host and reading elements one after another in the target. Sometimes I am unable to read elements at the same rate, I get a timeout in the middle and for the next read, I am able to read the element correctly. 

Will the elements be written one by one to FIFO even if I send as an array from Host?

Thanks in advance...

--

Citra

[crossrulz]

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@Citra wrote:

Will the elements be written one by one to FIFO even if I send as an array from Host?

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When you write an array to the DMA FIFO from the Host, the individual elements are added to the FIFO in order.  So if you are inserting more elements than your FIFO size, you will get an overflow error.  We would need to see code to verify if that is actually your issue.

[Citra]

CrossRulz,

I'm trying to write only 5 elements to the FIFO, though I have 1000 free elements in FIFO.

But when I read the FIFO in the target in an SCTL(200MHz), I read first 2 elements without error, then I get a timeout, after which I read next three elements without issue.

I tried reading FIFO length(remaining element to read) before reading the element, I get the following - 2,1,0(timeout),3,2,1

With slow rate(100MHz), the application works correctly. It seems the elements are added at a slow rate to FIFO. So, I'm trying to understand how the elements are added to FIFO.

----

Citra

[Intaris]

The elements are added at 100MHz IIRC, depending on the DRAM clock of your system.

For such a fast-running FIFO read, you'd better check that all of your required data is there before even starting to read them if you really need gapless reads.  200MHz is too fast to guarantee lossless transfer of data via DMA (as it's an asynchronous process).

[crossrulz]

Well, it does take time to add data to the FIFO.  And since your FPGA is running at such a fast rate, you are likely just going too fast for the RT to keep up.

Again, code here would help us help you with this issue.