FPGA FIFO

[Massif]

 Dear

In the project used a compact Rio with a NI9411 slot.

I would like recieved on the host by the FIFO the data acquire on the FPGA.

Fifo config : Arbitrated if multiple requestors only.

                    Delph: 8191 (default value)

I have always this error message and I don't understand where is the mistake.

Error -50400 occurred at _nirio_device_fifoRead.vi:2

The transfer did not complete within the timeout period or within the specified number of retries.

If someone can help me ;).

I have attache the project

[Nick_CH]

Dear,

Generally Underfow occures if there is not enough data present to read before the timeout expired and the Host FIFO Read Noed generates error –50400. You can change several things to solve the problem:

• Increase timeout
• Read Slower
• Read smaller sete of elements 

However, we use the DMA FIFO to transfer data between the target and the Host over the PCI bus. That means, when you are using a cRIO Architecture, between the FPGA and the Real-Time Controller.

In your case, you try to communicate directly between the FPGA and the Windows host using the DMA FIFO method. THAT’S NOT POSSIBLE.

You must mode the Host VI under the cRIO in your project.

Best regards

Nick_CH

Message Edited by Nick_CH on 03-18-2008 11:55 PM

[Massif]

 Dear Nick,

Thank you for your response.

My application is develloped on the compact rio, but after this application will be used between an Host and a Digital R Series Intelligent DAQ Devices.

If I developped the application on a cRIO (data transfer between FPGA and RT target=host VI ), can I after used the same application with an R series (data transfer between FPGA and "Windows My computer"=host VI)?

Regards

   Julien 

[Nick_CH]

Dear Julien,

Your are able to develop your application with the CompactRIO and then to reuse the code for your R-Series Target. A tutorial can help you to do it: How Can I Move my FPGA Application to a New Target?

However that means also that you must recompile your code for the R-Series.

BE CAREFUL: Several problems can occur when transferring code to the new target. It is possible that the new FPGA Target does not support the I/O resource, does not support the clock resource, does not support the FPGA FIFO or does not FPGA Memory.

With my personal experience, I never have problem with reusing one code on a new FPGA Target.

Best regards,

Nick_CH 

[captain_only]

Hey there Massif,

I took a peek at your project, and I have a couple reccomendations.

On the FPGA, you write to the DMA FIFO with timeout of 0. When you do this, you should handle the overflow case. This is especially true inside the single-cycle loop. The project you posted attempts to push data faster than the PCI bus is capable of carrying! (40Mhz * 4 bytes = 160MB/s, verses PCI maximum throughput of 133MB/s)  You are likely overflowing the FIFO and losing data for that reason. A simple fix would be to build a counter that increments only when the FIFO write node didn't timeout.

On the host, I noticed that you "configure" the FIFO after data has started flowing. This is entirely legal, but it would be better to do the configure before data is flowing to get the most reliable results, especially when you have an application that is sensitive to overflow!

I'd also like to clarify something from Nick_CH's post: It is possible to communicate with a DMA FPGA FIFO from a remote host, just like in Massif's example. Behind the scenes, we take care of DMA'ing data to the controller, and then transferring the data over the network. We do this so that an application written under "My Computer" can be moved to an RT controller with no code changes. It doesn't behave the same of course. It uses the network and so isn't deterministic and has much lower throughput.

I hope this helps!

Message Edited by captain_only on 03-19-2008 03:44 PM

[Nick_CH]

Hi Captain,

Many thanks for your input

Best regards,
Nick_CH

[Massif]

   Hi Captain!

Many thanks for your help. Theses informations are very important for my project.