FPGA compile error with Memory Write to 1-bit object

[RonW]

I get a compile error when accessing a single-bit boolean memory object from within an FPGA VI.

I'm running LabVIEW 8.5 on a cRIO-9014 CPU with a cRIO-9104 chassis.

I created a boolean memory object with a depth of one under the FPGA target, initialized to zero, with read and write arbitration if multiple requestors only.

If I create an FPGA VI that writes to address 0 of this object (and does nothing else), I get a compile error, as follows...

Regenerating IP...
ERROR:coreutil - Failure to set parameters on core: Illegal combination: Port A
   Width and Port A Depth
ERROR:coreutil - Failure to generate output products
ERROR:coreutil - An error occurred while running Java. Please examine the
   console or coregen log file for a specific IP related error.
   If there is no specific error the problem may be due to memory limitations.
   For more information please consult solution record 21955 available from:
   http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=21955Finished Regenerating.
ERROR:sim:57 - Error found during generation

If I change the memory object depth to 8, then the VI compiles, so I guess I'll do that for now. Does anyone know what's going on here?

[Aashish_M]

Hi RonW,

Xilinx doesn't support a depth of 1. If possible carry on using a deoth of 8 or use some other "register" to hold the value such as locals, globals, fifos, feedback nodes, etc...

This was reported to R&D (#49515 CAR ID) for further investigation.

Thanks for the feedback!

[RonW]

I used a depth of 2, which compiles fine. I want to implement mutexes, so I need a bit that I can access with a non-reentrant VI (to test and set it) and also externally (to reset it). It turns out I need a couple of mutexes, so the extra bit isn't wasted.