Question about cRIO 9004 resources

[TCPIP]

  I am writing a FPGA VI and need to download it to cRIO 9004 to generate bitstream, I need to use LUT( look up table) in my VI as the FPGA VI cannot calculate the sine function so I need to contruct a LUT in order to do the sine calculation inside the FPGA VI. However, after I contruct 2 LUT with size 2048, it shows there is not enough resources and the compliation is failed, what is the maximum sizes of the 2 LUTs in the FPGA VI so that the FPGA resources of LUT will be enough for use.

  At the same time, I want to know does using LUT also consumes the FPGA resources of SLICES, not just the FPGA resources of LUT? 

[griffindore]

Hi TCPIP,

The size of LUT that FPGA can use depends on the data type. It also depends on whether you have other Memory or FIFOs. LUTs do have some overhead with slices on the FPGA. This overhead does not change with the size of the LUT however. From the cRIO datasheet, the cRIO 9101 and 9102 have 82 kB of RAM and the cRIO 9103 and 9104 have 196 kB of RAM.

When I compile an FPGA VI for a cRIO 9102 with a 16 kB Look-Up Table, I get the following utilization output on my compilation.

  Number of RAMB16s                         8 out of 40     20%

This notifies that I have used eight 2 kB memory storage blocks out of the 40 available. I recommend looking at the utilization output to see which resources are running out. You may also want to take a look at the following links.

What is the Definition of Logic Cells, Logic Slices, Configurable Logic Blocks and Gates in Regards to FPGA Devices? 

FPGA Utilization Table 

[TCPIP]

  Apart from the overuse of the number 4 LUTs, sometimes, I also have the experience of overusing the resources of SLICES, does NI have the utilization table of resources SLICES, similar to the utilization table of the number 4 LUTs in the homepage of http://sine.ni.com/devzone/cda/epd/p/id/3257   ?

I am using cRIO 9004 with LabVIEW 8.2,  Thank you!

[griffindore]

Hi TCPIP,

In the utilization table, it represents how much of the FPGA fabric each function takes up. You can assume that it represents slices.

From the first link I posted above, "A logic cell consists of a lookup table, a flip flop, and connection to adjacent cells. The lookup table uses combinatorial logic to implement a 4-input expression (and, or, nand, addition, etc.)" These lookup tables are the number 4 LUTs you are running out of. These are seperate from the 1D Look-up Table you asked about originally. To reduce the amount of number 4-LUTs you are using, reduce combinatorial logic and arithmetic, reduce the size of your constants, controls, and indicators (i.e. change 32-bit to 16-bit or 8-bit), and use Single-Cycle Timed Loops (SCTL).

For more information on optimizing FPGA resources see the following link.
How Can I Optimize/Reduce FPGA Resource Usage?

I've also seen that you've posted the same questions on multiple threads. For future reference, please post your questions on only one thread. Thanks and I hope this information helps!