FPGA to Host best data transfer method

[zermelo]

 Hello to eveyrone:

I'm adapting the "General Auto PID simulator" to be used as a Host vi of a FPGA VI which is going to run in a NI RIO 7833R. I would want the data transfer to happen at a 200 KHz rate , which is the maximum rate for the ADC, and I need the Host and the FPGA  VI to be synchronized. I'm thinking about the method to use for transfer data from FPGA to Host.

The main thing is that the value of a boolean indicator has to be sent from the FPGA VI to the Host, so I'm forced to discard DMA FIFOs methods. Do you think that is possible to achieve that 200KHz with an interrupt method? Is there any other option avaliable?

Thank you a lot.

[Christian_L]

I'm not sure why you need the data transfer at 200 kHz since the PID routine on the host will not be able to run this fast. Depending on the speed of the host processor the maximum PID rate will be around 20-60 kHz.

The easiest method to use FPGA for I/O and to use the host application for PID control is to free run the input and output operations on the FPGA (let them run as fast as possible in a While loop and post the input values on the front panel/read the output values from the front panel of the FPGA VI). In the host VI you specify the timing of your control loop so that the host processor can keep up with the loop rate. In the loop on the host you read the latest input values from the FPGA VI, pass them to the PID VI, and then write the PID output back to the front panel of the FPGA VI so that they are written to the analog outputs on the next iteration of the FPGA loop.

If you do need true synchronization of the host loop with the FPGA, i.e. you want to control the timing of the host loop from the FPGA, you can use interrupts up to about 40 kHz. Using interrupts will have more overhead in the FPGA to host communication at that rate and will keep the host processor busy most of the time at this rate. An alternative to using interrupts is to set a Boolean indicator on the FPGA after new data has been acquired and poll (read) this value from the host. When the host sees that new data is available it reads the data, runs the PID, and updates the outputs. You need to reset the New Data Boolean flag in this process as well. Then the host goes back to waiting for the next new data. While the host is polling the New Data Boolean flag it should include some Wait time to release the processor to other processes/VIs running on the host.

[Christian_L]

I have attached a couple of simple LV8 examples showing the two methods I described above.

[zermelo]

Thanks for the reply and also for the  flies Christian: the information you gave me was very clear . But I guess I omitted something important: the PID is running in the FPGA, so I do not use the target only for I/O. Your recommendations are the same for this case?

Thanks for your attention
zermelo

[Christian_L]

In this case can you describe what operations you want to perform in the host application. Why does the host application need to be synchronized to the FPGA VI?

Using the polling method you can still synchronize the FPGA and host at 200 kHz, but you won't be able to perform a lot of processing on the host as much of the processor bandwidth will be used up by the synchronization process.