timed loop in a lvmodel

[mor8899]

I have built this vi. and the compiled model lvmodel and I am trying to execute that in Veristand and I have this error I know is a problem with de timed loop  because without it de program works  how can I use the loop and don't have this error?

[Pie566942.0]

The VeriStand engine provides the looping structure for the models in the system definition.  In other words, in general, LabVIEW models should not contain loops.  Ask yourself, how will the LabVIEW model yield to VeriStand if it's looping?  Can you post your model VI?

-Steve K

[mor8899]

This is a simplification of my model everything it's inside a while loop I tried to compile it without using the while looop and I have this error

Possible reason(s):

LabVIEW:  Generic error.
=========================
NI VeriStand:  NI VeriStand Gateway.lvlib:VeriStand Server Wrapper.vi >> NI VeriStand Server.lvlib:NI VeriStand Server.vi
<append>=========================
NI VeriStand:  Internal Error: Gateway Engine initialization timeout.

Engines that timed out:
Data Engine.vi
Can I use flat structures? Can I use wait?

[Pie566942.0]

I suggest you try your LabVIEW model in an otherwise empty system definition, i.e. ensure the error is related to this LabVIEW model. Yes, you can use Flat Sequence Structures.  No, you should not use Wait nodes inside LabVIEW models.  If you want to execute the model at a different rate from the Primary Control Loop (the PCL rate is defined on the Controller page of the system definition), then you should specify a "Decimation" in the Model Settings section of the LabVIEW model in the system definition.  For example, if the PCL is 1KHz, and you set the LabVIEW model decimation to 4, then the LabVIEW model runs at 250Hz.  The correct way to execute code on the execution target in parallel to the VeriStand engine at some arbitrary rate is to use an asynchronous custom device.  Things inside the VeriStand engine should run at, or at a decimation of, the Primary Control Loop rate.

-Steve K

[Pie566942.0]

I recommend you study this page if you haven't already: http://zone.ni.com/reference/en-XX/help/372846G-01/veristand/understanding_vs_engine/.

-Steve K