12-22-2011 03:14 PM
Hello,
I am new to Veristand and need help getting reflective memory working properly. I am currently running Veristand 2011 on 2 RT machines using the Fanuc 5565 reflective memory cards. I set up a read and write for reflective memory between the 2 RT machines. Machine A has the read and machine B has the write. I have each channel set to a specific memory address (x4000) with the same data type (double). When I run the system definition file, I don’t use a model, I’m just checking for communication, I have a Numeric control on machine B's channel and a Numeric Indicator on machine A's channel. My thought is that using the control, i can change the value stored at memory location x4000 and have the Indicator show the corresponding change. However, nothing happens when I increase or decrease the control. Any thoughts?
Thanks,
Matt
12-23-2011 02:31 PM
You might want to read these steps through before performing any of them in case there's one that catches your eye.
Check:
If this process doesn't work, then please post:
Steve K
02-13-2012 11:34 AM
Hello,
I recently spent hours getting Veristand to communicate with another machine that wasn't Veristand through Reflective Memory. My conclusion was that the method of creating variables that Veristand will write to the Reflective Memory is different from creating read variables. I notived that this was from around 2 months ago and won't go into more detail unless this is still an issue and in which case I can provide steps to get the Veristand Reflective Memory up and working because the documentation provided is lacking detail.
04-05-2014 08:58 AM
Hi MBoyd
As your self I am currrently usingVeristand 2013 on 2 RT machines using the Fanuc 5565 reflective memory cardsand I have the same issue with you.
While I can see the variables (acceleration measurements) written in the RM in the 1st controller I can not see these measurements to the second transfered to the 2nd. Can you explain how did you overcome this problem?
Many Thanks
Ilias
04-05-2014 11:56 AM
04-05-2014 01:53 PM
Hi Stephen
I think I now understand which my mistake is.
I am defining channels to both Reflective memories (with the same addresses) but I am not mapping them thinking that since the addresses are the same the information into one RM also appears to the second. I will try this next week and hopefully it will work.
I will let you know the outcome.
Thak you for your help
Ilias
04-05-2014 03:02 PM
04-05-2014 06:58 PM
So what you mean is that when we map normal channels between the 2 targets (such as inport/outports of a model deployed to target 1 to the channels of AO and AI Cards at target 2), Veristand automatically creates the links through the RM network.
04-05-2014 07:07 PM
04-05-2014 07:14 PM
Thanks Stephen. So simple but a bit confussing when you just start to work with RM networks.
Thanks for your help.
Ilias