Hello,
We have a veristand R4 project running on 3 parralel Linux RT targets (PXIe 8861).
On this project are declared several Hardware boards, models as well as several custom devices.
Some of these VCDs are "inline".
Sometimes, trying to re-deploy too quickly leads to an error.
We have then added UDP debug traces in some of the VCD's "close" steps.
We can now notice, using wireshark, that when the undeploy action is triggerd, versitand status switches immediatly to "Idle" whereas "close" steps are still being processed.
Veristand notifies neither the success of these steps nor the fails.
Is there a way to let veristand wait for the end of the process before switching to idle?
