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Veristand frequency

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Hello, 

I use a compactRIO with a voltage input module. I have to measure speed with an hall sensor until 10 kHz (square signal). I connect the module with the scan engine Ethercat. I have directly put bloc in veristand to do a counter, however the module gives information only each 0.01 s. So it's too slow for my operation. The counter works in 10 kHz. So if somone knows where I can change the speed information given by the module?

The module is an NI 9205 and it can reach 250 kHz (in the datasheet).

Thank you for your help.

 

Leo

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Hi Leo,

 

I ran into something similar with a DI counter.  It seems that VeriStand will only poll the I/O card at the RT loop rate (i.e 1000hz).  I had to write a custom FPGA code to run my counter at a faster rate then report it up to the VS engine independent of the Scan engine addon I was using.  You can do this while still using the Scan Engine addon if needed (this is what I did).  I think newer versions of VeriStand let you use waveforms, and this might work for you (have the card count, then send up the data every RT loop cycle).  Hope that helps.

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Thank you for your quick answer. So to write a fpga code I have to use Labview or Matlab and after export to Veristand? Maybe do you have a link that can explain to me? Thank you.

 

Leo

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Solution
Accepted by topic author Grusta07

You will need to have FPGA as part of labview to do this.  If you haven't done FPGA programming there will be a learning curve.  Here is a link

https://knowledge.ni.com/KnowledgeArticleDetails?id=kA03q000000YGlLCAW&l=en-US

 

I am assuming you are using the EtherCAT Scan engine addon.  

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Before you go down the FPGA route.  Look at Chassis->DAQ->Waveform Tasks in your System Explorer.

 

This looks like it will allow your to sample at your 10K.  You will have to read up on this since I have never used it.

 

 

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Thank you for this very good link.

Just one question, I saw that veristand 2021 works 64 bits. To use labview with the compactRIO I have to take the 32 bits 2021. But I saw somewhere that veristand works only with labview 64 bits (to convert model to veristand). For this operation it's working to have labview 32 bits?

 

 

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What I read is that you have to develop and build your FPGA in 32-bit LabVIEW and once you have your bit file, you can use that with VeriStand since the bit file itself doesn't run in VeriStand (it runs on the FPGA itself).

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